# US 5,703,580 A · Apparatus for encoding and decoding run length limited code data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,580 A - Document ID: US5703580A - Status: Granted - Kind: A - Application number: 08/678,601 - Filed: 1996-07-15 - Granted: 1997-12-30 - Earliest claimed: 1995-08-09 - Assignees: Samsung Elecrtronics Co., Ltd. - Inventors: Jung-wan Ko - Web page: https://patentgrep.com/patent/US5703580A ## CPC - H03M 5/145: {Conversion to or from block codes or representations thereof} - H04N 19/13: Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC] - H04N 19/60: using transform coding - H04N 19/91: Entropy coding, e.g. variable length coding [VLC] or arithmetic coding - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract The present invention relates to an apparatus for modulating input data by encoding the data to a run length limited (RLL) code data satisfying the (d,k,m,n) condition and decoding the modulated data, in which d is a minimum run length, k is a maximum run length, m is the bit number of input code data, n is the bit number of transmission code data, and the encoding and decoding apparatus according to the present invention comprises a look-up table (LUT) for encoding input parallel m-bit code data to r-bit code data in which r is not less than m and less than n, a post-encoder for encoding the encoded r-bit data to an n-bit transmission code data, a pre-decoder for decoding the input n-bit transmission code data to the r-bit code data according to the minimum run length condition, and a LUT for decoding the decoded r-bit code data to the original m-bit code data, by which the transmission code length is shortened according to the minimum run length condition so that the memory size required for encoding and decoding RLL code data can be reduced. ## Claims ### Claim 1 A decoding apparatus for run length limited (RLL) code data satisfying a (d,k,m,n) condition, in which d is a minimum run length, k is a maximum run length, m is the number of bits of input code data, and n is the bit number of bits of transmission code data, said decoding apparatus comprising: pre-decoding means for decoding input parallel n-bit transmission code data to r-bit code data in which r is not less than m and less than n, wherein r is set according to said minimum run length condition d; and decoding means for decoding said r-bit code data to m-bit code data. ### Claim 2 (depends on 1) A decoding apparatus for RLL code data as claimed in claim 1, wherein said pre-decoding means comprises at least one mapper which can reduce an input word length to an output word length as shown in the following Table 1: TABLE1 ______________________________________ d i j reduction ratio ______________________________________ 1 4 3 3/4 2 3 2 2/3 3 5 3 3/5 4 6 3 1/2 5 9 4 4/9 6 10 4 2/5 7 11 4 4/11 8 12 4 1/3 9 16 5 5/16 10 17 5 5/17 11 18 5 5/18 12 19 5 5/19 13 20 5 1/4 14 21 5 5/21 15 22 5 5/22 16 23 5 5/23 17 24 5 5/24 18 25 5 1/5 ______________________________________ according to said minimum run length condition. ### Claim 3 (depends on 2) A decoding apparatus for RLL code data as claimed in claim 2, wherein said mappers comprise a logic circuit. ### Claim 4 (depends on 2) A decoding apparatus for RLL code data as claimed in claim 2, wherein said mappers comprise one or more look-up tables. ### Claim 5 (depends on 2) A decoding apparatus for RLL code data as claimed in claim 2, wherein said pre-decoding means comprises a combination of mappers such that the sum of the output word lengths of the mappers can be minimized. ### Claim 6 (depends on 2) A decoding apparatus for RLL code data as claimed in claim 2, wherein said pre-decoding means comprises a combination of mappers having a minimum input word length for each mapper. ### Claim 7 (depends on 1) A decoding apparatus for RLL code data as claimed in claim 1, further comprising converting means for converting input transmission code data into said n-bit parallel transmission code data and for transmitting the converted parallel transmission code data to said pre-decoding means. ### Claim 8 (depends on 1) A decoding apparatus for RLL code data as claimed in claim 1, wherein said decoding means comprises a look-up-table of 2.sup.r .times.m bit size. ### Claim 9 (depends on 1) A decoding apparatus for RLL code data as claimed in claim 1, wherein said RLL code satisfies the (d,k,m,n) condition of (2,12,8,15). ### Claim 10 (depends on 9) A decoding apparatus for RLL code data as claimed in claim 9, wherein said pre-decoding means comprises a plurality of 3-to-2 mappers. ### Claim 11 (depends on 10) A decoding apparatus for RLL code data as claimed in claim 10, wherein said pre-decoding means reduces the word length of the transmission code data from 15 bits to 10 bits. ### Claim 12 (depends on 1) A decoding apparatus for RLL code data as claimed in claim 1, wherein said RLL code satisfies the (d,k,m,n) condition for eight to fourteen modulation code data of (2,10,8,14). ### Claim 13 (depends on 12) A decoding apparatus for RLL code data as claimed in claim 12, wherein said pre-decoding means comprises a plurality of 3-to-2 mappers. ### Claim 14 (depends on 13) A decoding apparatus for RLL code data as claimed in claim 13, wherein said pre-decoding means reduces the word length of the transmission code data from 14 bits to 9 bits. ### Claim 15 (depends on 1) A decoding apparatus for RLL code data as claimed in claim 1, wherein said RLL code data satisfies the (d,k,m,n) condition of (2,10,8,16). ### Claim 16 (depends on 15) A decoding apparatus for RLL code data as claimed in claim 15, wherein said pre-decoding means comprises a plurality of 3-to-2 mappers and a 5-to-3 mapper. ### Claim 17 (depends on 16) A decoding apparatus for RLL code data as claimed in claim 16, wherein said pre-decoding means reduces the word length of the transmission code data from 16 bits to 11 bits. ### Claim 18 An encoding apparatus for run length limited (RLL) code data satisfying a (d,k,m,n) condition in which d is a minimum run length, k is a maximum run length, m is the number of bits of input code data, and n is the number of bits of transmission code data, said encoding apparatus comprising: encoding means for encoding parallel input m-bit code data to r-bit code data in which r is not less than said m and less than n; post-encoding means for encoding said encoded r-bit code data to n-bit transmission code data, wherein r is set according to said minimum run length condition d. ### Claim 19 (depends on 18) An encoding apparatus for RLL code data as claimed in claim 18, wherein said encoding means comprises a look-up table of 2.sup.m .times.r bits. ### Claim 20 (depends on 18) An encoding apparatus for RLL code data as claimed in claim 18, wherein said post-encoding means comprises at least one mapper with an input word length and with an output word length interchanged from the input and the output shown in the Table 1: TABLE1 ______________________________________ d i j reduction ratio ______________________________________ 1 4 3 3/4 2 3 2 2/3 3 5 3 3/5 4 6 3 1/2 5 9 4 4/9 6 10 4 2/5 7 11 4 4/11 8 12 4 1/3 9 16 5 5/16 10 17 5 5/17 11 18 5 5/18 12 19 5 5/19 13 20 5 1/4 14 21 5 5/21 15 22 5 5/22 16 23 5 5/23 17 24 5 5/24 18 25 5 1/5 ______________________________________ according to said run length condition. ### Claim 21 (depends on 20) An encoding apparatus for RLL code data as claimed in claim 20, wherein said mapper comprises a logic circuit. ### Claim 22 (depends on 20) An encoding apparatus for RLL code data as claimed in claim 20, wherein said mapper comprises one or more look-up tables. ### Claim 23 (depends on 18) An encoding apparatus for RLL code data as claimed in claim 18, wherein said RLL code satisfies the (d,k,m,n) condition of (2,12,8,15). ### Claim 24 (depends on 18) An encoding apparatus for RLL code data as claimed in claim 18, wherein said RLL code data satisfies the (d,k,m,n) condition of (2,10,8,14). ### Claim 25 (depends on 18) An encoding apparatus for RLL code data as claimed in claim 18, wherein said RLL code satisfies the (d,k,m,n) condition of (2,10,8,16). ### Claim 26 (depends on 18) An encoding apparatus for RLL code data as claimed in claim 18, said apparatus further comprising: a first converting means for converting input serial m-bit code data into said parallel m-bit code data and for transmitting the converted parallel m-bit code data to said encoding means; and a second converting means for converting the parallel n-bit transmission code data transmitted from said post-encoding means into serial n-bit transmission code data. ### Claim 27 An encoding and decoding apparatus for RLL code data satisfying a (d,k,m,n) condition in which d is a minimum run length, k is a maximum run length, m is the number of bits of input code data, n is the number of bits of transmission code data, said apparatus comprising: encoding means for encoding input parallel m-bit code data to r-bit code data in which r is not less than m and less than n; post-encoding means for encoding said r-bit code data to n-bit transmission code data; pre-decoding means for decoding said n-bit transmission code data to said r-bit code data according to said minimum run length condition d; and decoding means for decoding said decoded r-bit code data to said original m-bit code data.