# US 5,703,541 A · Ring oscillator with two inverters per unit inverter circuit

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- Number: US 5,703,541 A
- Document ID: US5703541A
- Status: Granted
- Kind: A
- Application number: 08/821,315
- Filed: 1997-03-20
- Granted: 1997-12-30
- Earliest claimed: 1995-06-05
- Assignees: Mitsubishi Denki Kabushiki Kaisha; Mitsubishi Electric Engineering Company Limited
- Inventors: Teruya Nakashima
- Web page: https://patentgrep.com/patent/US5703541A

## CPC

- H03K 3/0231: Astable circuits {(H03K3/0315 takes precedence)}
- H03K 3/03: Astable circuits
- H03K 3/0322: {with differential cells}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A ring oscillator shortens the delay time between consecutive delayed clock signals, and increases of the number of delayed clock signals, without changing the oscillation frequency f of the ring oscillator and the number of stages n of inverter in one loop, and holding the same control current/osclllation frequency. The ring oscillator has odd numbers of unit inverters, wherein the unit inverter comprises two serial circuits connected in parallel each comprising of P channel transistor and N channel transistor, constant current sources connected to P channel and N channel sides in these parallel circuits, respectively, which are controlled by a current control circuit.

## Claims

### Claim 1

Ring oscillator having odd numbers of unit inverters,
said unit inverters comprising:
first and second inverter portions connected between first and second nodes in parallel, each inverter portion including P channel transistor connected between said first node and an output node thereof outputting a clock signal, and N channel transistor connected between said second node and said output node the output from the output node of said first inverter portion in each stage circulated through the ring, the output from the output node of said second inverter portion in each stage circulated through the ring;
a first constant current source connected between a voltage source node and said first node; and
a second constant current source connected between a ground potential node and said second node.

### Claim 2

Ring oscillator having odd numbers of unit inverters,
said unit inverter comprising:
first and second inverter portions connected between a first node and a second node connected to a ground potential node in parallel, each inverter portion including P channel transistor connected between said first node and an output node thereof outputting a clock signal, and N channel transistor connected between said second node and said output node the output from the output node of said first inverter portion in each stage circulated through the ring, the output from the output node of said second inverter portion in each stage circulated through the ring; and
a constant current source connected between a voltage source node and said first node.

### Claim 3

Ring oscillator having odd numbers of unit inverters,
said unit inverter comprising:
first and second inverter portions connected between a first node connected to a voltage source node and a second node in parallel, each inverter portion including P channel transistor connected between said first node and an output node thereof outputting a clock signal, and N channel transistor connected between said second node and said output node the output from the output node of said first inverter portion in each stage circulated through the ring, the output from the output node of said second inverter portion in each stage circulated through the ring; and
a constant current source connected between a ground potential node and said second node.

### Claim 4 (depends on 1)

Ring oscillator of claim 1, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3 V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4.

### Claim 5 (depends on 2)

Ring oscillator of claim 2, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3 V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4.

### Claim 6 (depends on 3)

Ring oscillator of claim 3, wherein
clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3 V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4.

### Claim 7 (depends on 1)

Ring oscillator of claim 1, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.2, V.sub.3, V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3.

### Claim 8 (depends on 2)

Ring oscillator of claim 2, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.2, V.sub.3, V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3.

### Claim 9 (depends on 3)

Ring oscillator of claim 3, wherein clock signals are taken out of the output node of said first and second inverter portions in the order of V.sub.2, V.sub.3, V.sub.6, V.sub.7, V.sub.10, . . . V.sub.2(n-1)-1, V.sub.2n, V.sub.1, V.sub.4, V.sub.5, V.sub.8, V.sub.9, . . . V.sub.2(n-1), V.sub.(2n-1), V.sub.2, V.sub.3.