Fully differential self-biased signal receiver

An amplifier circuit comprising:

• a first transistor coupled between a first voltage terminal and a first node, and having an input coupled to a biasing node;
• a second transistor coupled between a second voltage terminal and a second node, and having an input coupled to said biasing node;
• a third transistor coupled between said first node and a third node, and having an input coupled to accept a first input signal;
• a fourth transistor coupled between said second node and a fourth node, and having an input coupled to accept said first input signal;
• a fifth transistor coupled between said first voltage terminal and said fourth node, and having an input coupled to said biasing node;
• a sixth transistor coupled between said fourth node and a fifth node, and having an input coupled to said biasing node, said fifth node being a first amplifier output having a first signal output proportional to the difference between said first input signal and second input signal;
• a seventh transistor coupled between said third node and said fifth node, and having an input coupled to said biasing node;
• an eighth transistor coupled between said second voltage terminal and said third node, and having an input coupled to said biasing node;
• a ninth transistor coupled between said first node and a sixth node, and having an input coupled to accept a second input signal;
• a tenth transistor coupled between said second node and a seventh node, and having an input coupled to accept said second input signal;
• an eleventh transistor coupled between said first voltage terminal and said seventh node, and having an input coupled to said biasing node;
• a twelfth transistor coupled between said seventh node and an eighth node, and having an input coupled to said biasing node, said eighth node being a second amplifier output having a second signal output proportionate to the difference between said first input signal and second input signal, and being complementary to said first amplifier output;
• a thirteenth transistor coupled between said sixth node and said eighth node, and having an input coupled to said biasing node;
• a fourteenth transistor coupled between said second voltage terminal and said sixth node, and having an input coupled to said biasing node;
• a first resistor coupled between said fifth node and said biasing node;
• a second resistor coupled between said eighth node and said biasing node, said first and second resistors forming a negative bias feedback circuit feeding said biasing node.

An amplifier having means to accept a power source comprising:

• a first differential input stage having a first input for accepting a first input signal and having a first input stage output;
• a second differential input stage having a second input for accepting a second input signal and having a second input stage output;
• each of said first and second input stages being formed in a dual manner having a lower input portion coupled to an upper input portion, said lower input portion including a first connection of at least one n-type transistor, said upper input portion including a second connection of at least one p-type transistor, said second connection being connected in a mirror image of said first connection;
• a first current source feeding said lower portion of each of said first and second input stages and having a first current source control input coupled to a bias;
• a second current source feeding said upper portion of each of said first and second input stages and having a second current source control input coupled to said bias;
• a first biasing stage coupled to said first input stage output and having a first biasing stage output and a first biasing stage control input coupled to said bias;
• a second biasing stage coupled to said second input stage output and having a second biasing stage output and a second biasing stage control input coupled to said bias;
• each of said first and second biasing stages being formed in a dual manner and having a lower input portion coupled to an upper input portion, said lower input portion including a third connection of at least one n-type transistor, said upper input portion including a fourth connection of at least one p-type transistor, said forth connection being connected in a mirror image of said third connection;
• a voltage divider coupled between said first biasing stage output and said second biasing stage output to generate said bias, said bias being a negative feedback signal for biasing said control inputs;
• a first output stage coupled to said first biasing stage output and having a first amplifier output;
• a second output stage coupled to said second input stage and having a second amplifier output;
• each of said first and second output stages being formed in a dual manner having a lower output portion coupled to an upper output portion, said lower output portion including a fifth connection of at least one n-type transistor, said upper output portion including a sixth connection of at least one p-type transistor, said sixth connection being connected in a mirror image of said fifth connection;
• said input, biasing and output stages and current sources all being energized by said power source.

A receiver circuit having a means to accept a power source and comprising:

• a complementary differential amplifier having a first amplifier input for accepting a first input signal, a second amplifier input for accepting a second input signal, a first amplifier pair of outputs, and a second amplifier pair of outputs;
• a complementary current source feedings said amplifier, said current source having a pair of current source inputs, each current source input coupled to a bias output;
• a complementary first biasing stage cross-coupled to said first amplifier pair of outputs, and having a first biasing stage input coupled to said bias output, and a first biasing stage output;
• a complementary second biasing stage cross-coupled to said second amplifier pair of outputs, and having a second biasing stage input coupled to said bias output, and a second biasing output;
• a bias circuit means coupled between said first biasing output and said second biasing output, said bias circuit producing said bias output, said bias output being a source of negative feedback;
• a complementary first output stage coupled to said first biasing output and having a first output stage output, said first output stage output producing a first signal voltage dependent upon the relation between said first input voltage and said second input voltage;
• a complementary second output stage coupled to said second biasing output and having a second output stage output, said second output stage output producing a second signal voltage dependent upon the relation between said first input voltage and said second input voltage and being complementary to said first output stage output.

A method for producing and using a self-bias voltage to bias at least one bias-input of a local circuit, said circuit having a pair of biasing stages, each of said biasing stages having a biasing output, said method comprising the steps of:

• coupling a bias circuit between said biasing outputs, said bias circuit producing said self-bias voltage;
• and
• coupling said self-bias voltage to said at least one bias-input;
• and wherein said local circuit having complementary outputs.

A method for producing and using a self-bias voltage to bias at least one bias-input of a local circuit, said circuit having a pair of biasing stages, each of said biasing stages having a biasing output, said method comprising the steps of:

• coupling a voltage divider between said biasing outputs,
• providing said divider with a divider output, said divider output producing said bias voltage;
• and
• coupling said self bias voltage to said at least one bias-input.

A device for producing and using a self-bias voltage to at least one bias input of a local circuit, said device comprising:

• a pair of biasing stages, each of said biasing stages having a biasing output,
• a bias circuit coupled between said biasing outputs, said bias circuit producing said self-bias voltage;
• and
• means for coupling said self-bias voltage to said at least one bias input;
• and wherein said device having complementary outputs.

An amplifier circuit comprising:

• a first transistor having a drain coupled to a first voltage terminal, a source coupled to a first node and a gate coupled to a biasing node;
• a second transistor having a drain coupled to a second voltage terminal and a source coupled to a second node and a gate coupled to said biasing node;
• a third transistor having a drain coupled to said first node and a source coupled to a third node and a gate coupled to accept a first input signal;
• a fourth transistor having a drain coupled to said second node, a source coupled to a fourth node and a gate coupled to accept said first input signal;
• a fifth transistor having a drain coupled to said first voltage terminal, a source coupled to said fourth node and a gate coupled to said biasing node;
• a sixth transistor having a drain coupled to said fourth node and a source coupled to a fifth node and a gate coupled to said biasing node, said fifth node being a first amplifier output having a first signal output proportional to the difference between said first input signal and second input signal;
• a seventh transistor having a drain coupled to said third node, a source coupled to said fifth node and a gate coupled to said biasing node;
• an eighth transistor having a drain coupled to said second voltage terminal, a source coupled to said third node and a gate coupled to said biasing node;
• a ninth transistor having a drain coupled to said first node, a source coupled to a sixth node and a gate coupled to accept a second input signal;
• a tenth transistor having a drain coupled to said second node, a source coupled to a seventh node and a gate coupled to accept said second input signal;
• an eleventh transistor having a drain coupled to said first voltage terminal and a source coupled to said seventh node and a gate coupled to said biasing node;
• a twelfth transistor having a drain coupled to said seventh node, a source coupled to an eighth node and a gate coupled to said biasing node, said eighth node being a second amplifier output having a second signal output proportional to the difference between said first input signal and second input signal and being complementary to said first amplifier output;
• a thirteenth transistor having a drain coupled to said sixth node, a source coupled to said eighth node and a gate coupled to said biasing node;
• a fourteenth transistor having a drain coupled to said second voltage terminal and a source coupled to said sixth node and a gate coupled to said biasing node;
• a first resistor coupled between said fifth node and said biasing node;
• a second resistor coupled between said eighth node and said biasing node, said first and second resistors forming a negative bias feedback circuit feeding said biasing node.

An amplifier circuit comprising:

• a first transistor having an emitter coupled to a first voltage terminal, a collector coupled to a first node and a base coupled to a biasing node;
• a second transistor having an emitter coupled to a second voltage terminal and a collector coupled to a second node and a base coupled to said biasing node;
• a third transistor having an emitter coupled to said first node and a collector coupled to a third node and a base coupled to accept a first input signal;
• a fourth transistor having an emitter coupled to said second node, a collector coupled to a fourth node and a base coupled to accept said first input signal;
• a fifth transistor having an emitter coupled to said first voltage terminal, a collector coupled to said fourth node and a base coupled to said biasing node;
• a sixth transistor having an emitter coupled to said fourth node and a collector coupled to a fifth node and a base coupled to said biasing node, said fifth node being a first amplifier output having a first signal output proportional to the difference between said first input signal and second input signal;
• a seventh transistor having an emitter coupled to said third node, a collector coupled to said fifth node and a base coupled to said biasing node;
• an eighth transistor having an emitter coupled to said second voltage terminal, a collector coupled to said third node and a base coupled to said biasing node;
• a ninth transistor having an emitter coupled to said first node, a collector coupled to a sixth node and a base coupled to accept a second input signal;
• a tenth transistor having an emitter coupled to said second node, a collector coupled to a seventh node and a base coupled to accept said second input signal;
• an eleventh transistor having an emitter coupled to said first voltage terminal and a collector coupled to said seventh node and a base coupled to said biasing node;
• a twelfth transistor having an emitter coupled to said seventh node, a collector coupled to an eighth node and a base coupled to said biasing node, said eighth node being a second amplifier output having a second signal output proportional to the difference between said first input signal and second input signal and being complementary to said first amplifier output;
• a thirteenth transistor having an emitter coupled to said sixth node, a collector coupled to said eighth node and a base coupled to said biasing node;
• a fourteenth transistor having an emitter coupled to said second voltage terminal and a collector coupled to said sixth node and a base coupled to said biasing node;
• a first resistor coupled between said fifth node and said biasing node;
• a second resistor coupled between said eighth node and said biasing node, said first and second resistors forming a negative bias feedback circuit feeding said biasing node.