# US 5,703,524 A · Piece-wise linear approximation of a dB linear programmable gain amplifier

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- Number: US 5,703,524 A
- Document ID: US5703524A
- Status: Granted
- Kind: A
- Application number: 08/631,900
- Filed: 1996-04-16
- Granted: 1997-12-30
- Earliest claimed: 1996-04-16
- Assignees: Exar Corporation
- Inventors: Xiaole Chen
- Web page: https://patentgrep.com/patent/US5703524A

## CPC

- G06J 1/00: Hybrid computing arrangements
- G06G 7/06: Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming {(hybrid computers G06J)}
- G06G 7/28: for synthesising functions by piecewise approximation
- G06J: HYBRID COMPUTING ARRANGEMENTS (optical hybrid computing devices G06E3/00)
- G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00)

## Abstract

A programmable gain amplifier which can be realized using CMOS transistors. The amplifier provides a plurality of linear gain segments, with each of the gain segments having a different gain. A particular combination of the gain segments are selected using a digital control input to give an approximation of a linear dB output. By appropriately choosing the segments and how they combine, an approximation that is accurate to the least significant bit of a digital system can be provided.

## Claims

### Claim 1

A programmable gain amplifier comprising:
a plurality of linear gain segments, each of said linear gain segments having a different gain;
a multiple bit digital control input; and
selection logic, coupled to said multiple bit digital control input, configured to selectively enable desired ones of said linear gain segments.

### Claim 2 (depends on 1)

The amplifier of claim 1 wherein said selection logic comprises:
first selection logic configured to select one of said linear gain segments; and
second selection logic configured to select a fraction to be applied to one of said gain segments.

### Claim 3 (depends on 2)

The amplifier of claim 2 wherein said second selection logic is coupled to larger linear gain segments for larger desired gain values.

### Claim 4 (depends on 2)

The amplifier of claim 2 wherein said second selection logic comprises an analog to digital converter.

### Claim 5 (depends on 1)

The amplifier of claim 1 further comprising a second plurality of linear gain segments arranged to provide a differential gain output.

### Claim 6 (depends on 1)

The amplifier of claim 1 wherein said amplifier comprises one stage of a multi-stage amplifier.

### Claim 7 (depends on 1)

The amplifier of claim 1 wherein said gain segments comprise a plurality of CMOS transistors having different sizes.

### Claim 8 (depends on 7)

The amplifier of claim 7 further comprising:
a current source;
first selection logic connected to direct current from said current source through a selected combination of said CMOS transistors; and
second selection logic connected to direct a selected fraction of current from said current source through one of said CMOS transistors not in said combination.

### Claim 9 (depends on 8)

The amplifier of claim 8 wherein said second selection logic is always coupled to a CMOS transistor having a larger size than the CMOS transistors in said combination.

### Claim 10

A programmable gain amplifier comprising:
a constant current source;
a plurality of CMOS gain transistors of different sizes;
a first plurality of switching transistors connected between said constant current source and said CMOS gain transistors;
a fractional current generating circuit coupled to said constant current source; and
a second plurality of switching transistors connected between said fractional current generating circuit and said plurality of CMOS gain transistors.

### Claim 11 (depends on 10)

The amplifier of claim 10 further comprising a digital control input having least significant bits coupled to said fractional current generating circuit and most significant bits coupled to said first and second plurality of switching transistors.

### Claim 12 (depends on 11)

The amplifier of claim 11 further comprising decoding logic coupled between said most significant bits of said digital control input and said switching transistors.

### Claim 13 (depends on 12)

The amplifier of claim 12 wherein said decoding logic always controls said second plurality of switching transistors to couple said fractional current generating circuit to a CMOS gain transistor having a larger size than any transistor in a combination of said CMOS gain transistors selected by said first plurality of switching transistors.

### Claim 14 (depends on 10)

The amplifier of claim 10 wherein said fractional current generating circuit comprises a digital to analog converter.

### Claim 15 (depends on 10)

The amplifier of claim 10 wherein said fractional current generating circuit is connected to a second current source, and supplies a constant current to said CMOS gain transistors, while varying the fraction of said constant current from said first current source.