# US 5,703,515 A · Timing generator for testing IC > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,515 A - Document ID: US5703515A - Status: Granted - Kind: A - Application number: 08/620,776 - Filed: 1996-03-22 - Granted: 1997-12-30 - Earliest claimed: 1995-04-20 - Assignees: Yokogawa Electric Corporation - Inventors: Akira Toyama; Kazuhiro Shimizu - Web page: https://patentgrep.com/patent/US5703515A ## CPC - H03K 5/131: Digitally controlled - G01R 31/31922: {Timing generation or clock distribution (G01R31/3191 takes precedence)} - G01R 31/31928: {Formatter (driver, receiver details G01R31/31924)} - H03K 5/156: Arrangements in which a continuous pulse train is transformed into a train having a desired pattern - G01R 31/3191: {Calibration} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A timing generator which receives a rate signal and generates an output signal based on the rate signal, and comprises at least two delay lines for causing delays in the rate signal, a formatter for receiving signals from the delay lines and for determining the rise and fall of an output signal according to such signals from the delay lines, and for generating an output signal, memories for storing delay time data from the delay lines, and a data selector for taking the delay time data from the memories and to switch the delay time data, whereby accurate timing signals are generated utilizing short skew adjustment time. ## Claims ### Claim 1 A timing generator for generating an output signal in accordance with a rate signal, comprising: at least two delay lines for delaying said rate signal; formatter means for receiving signals from said at least two delay lines, for determining rise and fall of an output signal by using said received signals, and for generating said output signal; memory means for storing delay time data for said at least two delay lines; and data selector means for supplying said delay time data from said memory means to said at least two delay lines by switching. ### Claim 2 (depends on 1) The generator of claim 1, wherein said formatter means comprises delay lines to adjust skews in an input stage thereof. ### Claim 3 (depends on 2) The generator of claim 2, wherein said data selector means comprises means for combining a first delay time data with a second delay time data used for adjusting skews, and means for supplying the combined delay time data to said at least two delay lines. ### Claim 4 (depends on 1) The generator of claim 1, further comprising an edge controller means for outputting rate signals to said at least two delay lines in accordance with pattern data and format data, respectively. ### Claim 5 (depends on 1) The generator of claim 1, wherein said formatter means comprises means for generating said output signal in accordance with a pattern data and a format data. ### Claim 6 (depends on 1) The generator of claim 1, wherein said formatter means comprises at least one SR flip flop circuit. ### Claim 7 A timing generator for generating an output signal in accordance with a rate signal, comprising: at least two delay lines for delaying said rate signal; formatter means for receiving signals from said at least two delay lines, for determining rise and fall of an output signal using said received signals, and for generating said output signal; and memory means for storing delay time data for use in said at least two delay lines, wherein said delay time data is applied from said memory means to said at least two delay lines through a switching function under instructions from changed address instructions. ### Claim 8 (depends on 7) The generator of claim 7, wherein said address instructions are carried out by an address data and a pattern data. ### Claim 9 (depends on 7) The generator of claim 7, wherein said formatter means comprises delay lines to adjust skews in an input stage thereof. ### Claim 10 (depends on 9) The generator of claim 9, wherein said memory means comprises means for combining a first delay time data with a second delay time data used for adjusting skews, and means for supplying the combined delay time data to said at least two delay lines. ### Claim 11 (depends on 7) The generator of claim 7, further comprising an edge controller means for outputting rate signals to said at least two delay lines in accordance with pattern data and format data, respectively. ### Claim 12 (depends on 7) The generator of claim 7, wherein said formatter means comprises means for generating said output signal in accordance with a pattern data and a format data. ### Claim 13 (depends on 7) The generator of claim 7, wherein said formatter means comprises at least one SR flip flop circuit. ### Claim 14 A timing generator for generating an output signal in accordance with a rate signal, comprising: at least two delay lines for delaying said rate signal; formatter means for receiving signals from said at least two delay lines, for determining rise and fall of an output signal by using said received signals, and for generating said output signal; memory means for storing delay time data of said at least two delay lines, wherein said delay time data from said memory means is supplied to said at least two delay lines by switching; and edge controller means for outputting rate signals to said at least two delay lines in accordance with pattern data and format data, respectively. ### Claim 15 (depends on 14) The generator of claim 14, wherein said formatter means comprises delay lines to adjust skews in an input stage thereof. ### Claim 16 (depends on 14) The generator of claim 14, wherein said memory means comprises means for combining a first delay time data with a second delay time data used for adjusting skews, and means for supplying the combined delay time data to said at least two delay lines. ### Claim 17 (depends on 14) The generator of claim 14, wherein said formatter means comprises means for generating said output signal in accordance with said pattern data and said format data. ### Claim 18 (depends on 14) The generator of claim 14, wherein said formatter means comprises at least one SR flip flop circuit. ### Claim 19 A timing generator for outputting a timing signal in accordance with a rate signal, said generator comprising: an edge controller means for receiving said rate signal and for outputting enable signals in accordance with pattern data and format data; four delay lines for receiving said enable signals from said edge controller means as input signals and for delaying said enable signals; formatter means comprising two OR gates, each of which receives outputs from a set of two of said four delay lines, and an SR flip flop circuit having a set terminal for receiving output from one of said OR gates and a reset terminal for receiving output from the other of said OR gates, and means for supplying an output signal from said SR flip flop circuit; and memory means for storing delay time data for said four delay lines, wherein said delay time data is supplied from said memory means to said four delay lines through switching.