# US 5,703,511 A · Charge pump circuit, PLL circuit with charge pump circuit, and semiconductor integrated circuit with charge pump circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,511 A - Document ID: US5703511A - Status: Granted - Kind: A - Application number: 08/735,997 - Filed: 1996-10-23 - Granted: 1997-12-30 - Earliest claimed: 1996-06-19 - Assignees: Fujitsu Limited - Inventors: Masaaki Okamoto - Web page: https://patentgrep.com/patent/US5703511A ## CPC - H03L 7/0895: {Details of the current generators (H03L7/0893 takes precedence)} - H03L 7/143: {by switching the reference signal of the phase-locked loop} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A charge pump circuit has a first transistor connected to a first power source and having a control electrode to receive a first control signal; a second transistor connected to a second power source and having a control electrode to receive a second control signal; a third transistor and a current source connected in series between the first and second transistors, a node between the third transistor and the current source providing a signal, which is passed through a low-pass filter to provide a VCO input signal; and a control voltage generator for generating a control voltage according to the VCO input signal and applying the control voltage to a control electrode of the third transistor. This charge pump circuit realizes a stable PLL operation for a wide range of VCO input voltages, has little data rate dependency, and operates at high speed. ## Claims ### Claim 1 A charge pump circuit comprising: a first transistor connected to a first power source line and having a control electrode to receive a first control signal; a second transistor connected to a second power source line and having a control electrode to receive a second control signal; a third transistor and a current source connected in series between the first and second transistors, a node between the third transistor and the current source providing a signal, which is passed through a low-pass filter to provide a VCO input signal; and a control voltage generator for generating a control voltage according to the VCO input signal and applying the control voltage to a control electrode of the third transistor. ### Claim 2 (depends on 1) A charge pump circuit as claimed in claim 1, wherein the first and second transistors are enhancement transistors, and the third transistor and current source are depletion transistors. ### Claim 3 (depends on 1) A charge pump circuit as claimed in claim 1, wherein the first to third transistors and current source are Schottky-junction field effect transistors. ### Claim 4 (depends on 1) A charge pump circuit as claimed in claim 1, wherein the first to third transistors and current source are metal-gate or silicon-gate field effect transistors, and at least one diode is arranged between the control electrode of the third transistor and the node. ### Claim 5 (depends on 1) A charge pump circuit as claimed in claim 1, wherein the control voltage generator has two cascaded level shifters and two bias generators having different temperature coefficients to set separate temperature characteristics for shifting levels of the level shifters. ### Claim 6 (depends on 1) A charge pump circuit as claimed in claim 1, wherein the control voltage generator has a positive-phase amplifier having feedback resistors to adjust a gain. ### Claim 7 A phase-locked loop circuit having a phase comparator for comparing phases of reference and output signals with each other, a charge pump circuit for receiving first and second control signals from the phase comparator and providing corresponding signals, a low-pass filter for filtering an output of the charge pump circuit into a VCO input signal, and a voltage-controlled oscillator for generating a signal whose frequency is determined by the VCO input signal, wherein the charge pump circuit comprises: a first transistor connected to a first power source line and having a control electrode to receive said first control signal; a second transistor connected to a second power source line and having a control electrode to receive said second control signal; a third transistor and a current source connected in series between the first and second transistors, a node between the third transistor and the current source providing a signal, which is passed through a low-pass filter to provide said VCO input signal; and a control voltage generator for generating a control voltage according to the VCO input signal and applying the control voltage to a control electrode of the third transistor. ### Claim 8 (depends on 7) A phase-locked loop circuit as claimed in claim 7, wherein the first and second transistors are enhancement transistors, and the third transistor and current source are depletion transistors. ### Claim 9 (depends on 7) A phase-locked loop circuit as claimed in claim 7, wherein the first to third transistors and current source are Schottky-junction field effect transistors. ### Claim 10 (depends on 7) A phase-locked loop circuit as claimed in claim 7, wherein the first to third transistors and current source are metal-gate or silicon-gate field effect transistors, and at least one diode is arranged between the control electrode of the third transistor and the node. ### Claim 11 (depends on 7) A phase-locked loop circuit as claimed in claim 7, wherein the control voltage generator has two cascaded level shifters and two bias generators having different temperature coefficients to set separate temperature characteristics for shifting levels of the level shifters. ### Claim 12 (depends on 7) A phase-locked loop circuit as claimed in claim 7, wherein the control voltage generator has a positive-phase amplifier having feedback resistors to adjust a gain. ### Claim 13 (depends on 7) A phase-locked loop circuit as claimed in claim 7, wherein the phase-locked loop circuit further comprises a clamp circuit for controlling the first control signal supplied to the control electrode of the first transistor, the clamp circuit receiving the VCO input signal and clamping an amplitude of the first control signal irrespective of a fluctuation in the VCO input signal. ### Claim 14 (depends on 13) A phase-locked loop circuit as claimed in claim 13, wherein the clamp circuit has an inverter, and a potential of the second power source line applied to the inverter is changed according to the VCO input signal. ### Claim 15 (depends on 7) A phase-locked loop circuit as claimed in claim 7, wherein the phase-locked loop circuit comprises a control signal processor arranged in front of the first and second transistors, to enhance the edges of the first and second control signals. ### Claim 16 (depends on 15) A phase-locked loop circuit as claimed in claim 15, wherein the control signal processor comprises: a first delay circuit for delaying the first control signal and supplying the delayed signal to the control electrode of the first transistor; a first chopper for generating a narrow pulse in response to a second edge of each pulse of the first control signal and using the pulse to enhance the second edge; a fourth transistor controlled by the output of the first chopper; a second delay circuit for delaying the second control signal and supplying the delayed signal to the control electrode of the second transistor; a second chopper for generating a narrow pulse in response to a second edge of each pulse of the second control signal and using the pulse to enhance the second edge; and a fifth transistor controlled by an output of the second chopper. ### Claim 17 (depends on 16) A phase-locked loop circuit as claimed in claim 16, wherein each of the first and second choppers includes an odd number of inverters and a two-input NOR gate, a corresponding one of the first and second control signals being supplied through the inverters to an input terminal of the NOR gate and directly to another input terminal of the NOR gate. ### Claim 18 A semiconductor integrated circuit having a multiplexer for multiplexing low-speed parallel data composed of a plurality of bits into high-speed serial data, a clock generator for receiving a reference clock signal and generating a clock signal for the multiplexer, a demultiplexer for demultiplexing high-speed serial data into low-speed parallel data composed of a plurality of bits, and a clock recovery circuit for receiving the high-speed serial data and generating a clock signal for the demultiplexer, wherein the clock recovery circuit includes a phase-locked loop circuit having a phase comparator for comparing the phases of reference and output signals with each other, a charge pump circuit for receiving first and second control signals from the phase comparator and providing corresponding signals, a low-pass filter for filtering an output of the charge pump circuit into a VCO input signal, and a voltage-controlled oscillator for generating a signal whose frequency is determined by the VCO input signal, wherein the charge pump circuit comprises: a first transistor connected to a first power source line and having a control electrode to receive said first control signal; a second transistor connected to a second power source line and having a control electrode to receive said second control signal; a third transistor and a current source connected in series between the first and second transistors, a node between the third transistor and the current source providing a signal, which is passed through a low-pass filter to provide said VCO input signal; and a control voltage generator for generating a control voltage according to the VCO input signal and applying the control voltage to a control electrode of the third transistor. ### Claim 19 (depends on 18) A semiconductor integrated circuit as claimed in claim 18, wherein the first and second transistors are enhancement transistors, and the third transistor and current source are depletion transistors. ### Claim 20 (depends on 18) A semiconductor integrated circuit as claimed in claim 18, wherein the first to third transistors and current source are Schottky-junction field effect transistors. ### Claim 21 (depends on 18) A semiconductor integrated circuit as claimed in claim 18, wherein the first to third transistors and current source are metal-gate or silicon-gate field effect transistors, and at least one diode is arranged between the control electrode of the third transistor and the node. ### Claim 22 (depends on 18) A semiconductor integrated circuit as claimed in claim 18, wherein the control voltage generator has two cascaded level shifters and two bias generators having different temperature coefficients to set separate temperature characteristics for shifting levels of the level shifters. ### Claim 23 (depends on 18) A semiconductor integrated circuit as claimed in claim 18, wherein the control voltage generator has a positive-phase amplifier having feedback resistors to adjust a gain. ### Claim 24 (depends on 18) A semiconductor integrated circuit as claimed in claim 18, wherein the semiconductor integrated circuit further comprises a clamp circuit for controlling the first control signal supplied to the control electrode of the first transistor, the clamp circuit receiving the VCO input signal and clamping an amplitude of the first control signal irrespective of a fluctuation in the VCO input signal. ### Claim 25 (depends on 24) A semiconductor integrated circuit as claimed in claim 24, wherein the clamp circuit has an inverter, and a potential of the second power source line applied to the inverter is changed according to the VCO input signal. ### Claim 26 (depends on 18) A semiconductor integrated circuit as claimed in claim 18, wherein the semiconductor integrated circuit comprises a control signal processor arranged in front of the first and second transistors, to enhance the edges of the first and second control signals. ### Claim 27 (depends on 26) A semiconductor integrated circuit as claimed in claim 26, wherein the control signal processor comprises: a first delay circuit for delaying the first control signal and supplying the delayed signal to the control electrode of the first transistor; a first chopper for generating a narrow pulse in response to a second edge of each pulse of the first control signal and using the pulse to enhance the second edge; a fourth transistor controlled by the output of the first chopper; a second delay circuit for delaying the second control signal and supplying the delayed signal to the control electrode of the second transistor; a second chopper for generating a narrow pulse in response to a second edge of each pulse of the second control signal and using the pulse to enhance the second edge; and a fifth transistor controlled by an output of the second chopper. ### Claim 28 (depends on 27) A semiconductor integrated circuit as claimed in claim 27, wherein each of the first and second choppers includes an odd number of inverters and a two-input NOR gate, a corresponding one of the first and second control signals being supplied through the inverters to an input terminal of the NOR gate and directly to another input terminal of the NOR gate.