# US 5,703,505 A · Signal reception apparatus having automatic level selection function

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- Number: US 5,703,505 A
- Document ID: US5703505A
- Status: Granted
- Kind: A
- Application number: 08/369,456
- Filed: 1995-01-06
- Granted: 1997-12-30
- Earliest claimed: 1994-11-09
- Assignees: Goldstar Electron Co., Ltd.
- Inventors: Ki Jo Kwon
- Web page: https://patentgrep.com/patent/US5703505A

## CPC

- H03K 5/082: {with an adaptive threshold}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A signal reception apparatus has an automatic level selection function. A comparing circuit compares a level of an input signal with a plurality of sensing levels and outputs a plurality of sensing signals in accordance with the compared result. An auto select level controller receives the plurality of sensing signals from the comparing circuit and selects one of the plurality of sensing levels in response to the plurality of sensing signals. The auto select level controller includes a plurality of flip flop stages. Each of the plurality of flip flop stages has a plurality of flip flops connected in series and is coupled to a corresponding one of the plurality of sensing signals from the comparing circuit. A circuit receives the output signals from the plurality of flip flop stages and selects one of the plurality of sensing levels in response to the inputted sensing signals.

## Claims

### Claim 1

A signal reception apparatus having automatic level selection function, comprising:
a plurality of comparing means, each for comparing a received input signal with one of a plurality of sensing levels of said input signal and each outputting a sensing signal in accordance with such a comparison;
auto select level control means for receiving said sensing signal from each of said plurality of comparing means for generating a reception enable signal according to the sensing signal which is selected by said auto select level control means; and
a first data buffer for receiving the sensing signal from one of said plurality of comparing means and outputting the received sensing signal as valid reception data in response to the reception enable signal from the auto select level control means.

### Claim 2 (depends on 1)

The signal reception apparatus according to claim 1, wherein said auto select level control means includes:
a plurality of flip flop stages, each of said plurality of flip flop stages having a plurality of first flip flops connected in series and each flip flop stage being coupled to a corresponding one of said plurality of sensing signals from said comparing means; and
means for selecting an output signal from said plurality of flip flop stages and generating said reception enable signal according to said one of said output signals from said plurality of said flip flop stages.

### Claim 3 (depends on 2)

The signal reception apparatus of claim 2, wherein said receiving means comprises:
circuitry, coupled to receive output signals from said flip flop stages, that performs a logical operation on the output signals of said flip flop stages;
a plurality of second data buffers, each second data buffer receiving a corresponding one of said plurality of sensing signals, and outputting the corresponding one of said plurality of sensing signals in response to a corresponding output signal of said logic circuitry;
a logic gate coupled to said plurality of second data buffers such that a logical operation is performed on the outputs of said plurality of second data buffers; and
a second flip flop, coupled to said logical gate, for outputting the reception enable signal.

### Claim 4

A signal reception apparatus comprising:
a plurality of comparators, each comparator comparing a first input signal with one of a plurality of second input signals;
a control circuit receiving signals outputted by said plurality of comparators to generate an enable signal, wherein said control circuit includes a plurality of first logic gates and a plurality of flip flop stages, each flip flop stage receiving a logical output of a corresponding first logic gate which has performed a logical operation on said signals outputted from said plurality of comparators; and
means, coupled to one of said plurality of comparators and said control circuit, for generating one of said signals outputted from said plurality of comparators as an output signal in response to the enable signal of said control circuit.

### Claim 5 (depends on 4)

The signal reception apparatus of claim 4, wherein said control circuit further includes
logic circuitry, coupled to receive output signals from said flip flop stages, that performs a logical operation on the output signals of said flip flop stages;
a plurality of first data buffers, each first data buffer receiving a corresponding one of said signals from said plurality of comparators, and outputting the corresponding one of said signals of said plurality of comparators in response to a corresponding output signal of said logic circuitry;
a second logic gate coupled to said plurality of first data buffers such that a logical operation is performed on the outputs of said plurality of first data buffers; and
a further flip flop, coupled to said second logic gate, for outputting the enable signal in response to an output of the second logic gate.

### Claim 6 (depends on 5)

The signal reception apparatus of claim 5, wherein said control circuit generates the enable signal based on the signals outputted by said plurality of comparators.

### Claim 7 (depends on 6)

The signal reception apparatus of claim 6, wherein said generating means comprises a second data buffer coupled to one of said comparators and said control circuit, wherein said second buffer responds to said enable signal such that one of said outputs of said plurality of comparators is outputted by the signal reception apparatus.

### Claim 8 (depends on 7)

The signal reception apparatus of claim 7, wherein each flip flop stage comprises a plurality of flip flops coupled in series, and said logic circuitry receives an output from each of said series coupled flip flops.