# US 5,703,500 A · Threshold voltage scalable buffer with reference level

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- Number: US 5,703,500 A
- Document ID: US5703500A
- Status: Granted
- Kind: A
- Application number: 08/648,443
- Filed: 1996-05-15
- Granted: 1997-12-30
- Earliest claimed: 1996-05-15
- Assignees: Micron Technology, Inc.
- Inventors: Huy Thanh Vo
- Web page: https://patentgrep.com/patent/US5703500A

## CPC

- H03K 19/018521: {of complementary type, e.g. CMOS}
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).

## Claims

### Claim 1

A buffer circuit, comprising:
a first inverter with a first current limiter that limits the standby current used by the first inverter;
a second inverter coupled to an output of the first inverter so as to convert a first logic level of an input signal provided to the first inverter to a second logic level at an output of the second inverter;
a second current limiting circuit coupled to an output of the first inverter and coupled an input of the second inverter to further limit the standby current in the buffer; and
wherein the first current limiting circuit comprises first and second transistors each having a gate coupled to receive the output signal of the second inverter such that the first transistor limits the standby current of the first inverter when the output of the buffer is a low logic level and the second transistor limits the standby current of the buffer when the output of the buffer is a high logic value.

### Claim 2

A buffer circuit, comprising:
a first inverter with a first current limiter that limits the standby current used by the first inverter;
a second inverter coupled to an output of the first inverter so as to convert a first logic level of an input signal provided to the first inverter to a second logic level at an output of the second inverter;
a second current limiting circuit coupled to an output of the first inverter and coupled to an input of the second inverter to further limit the standby current in the buffer; and
wherein the second current limiting circuit comprises:
a current limiting transistor with a drain coupled to the output of the first inverter and the input of the second inverter in a standby current path for the buffer circuit; and
a reference voltage is coupled to the source of the current limiting transistor that establishes a low gate to source voltage for the transistor so as to limit the standby current.

### Claim 3 (depends on 2)

The buffer of claim 2; wherein the second current limiting circuit further comprises a voltage generator circuit that generates a reference voltage that is approximately equal to a logic level of the input signal.

### Claim 4 (depends on 3)

The buffer of claim 3, wherein the voltage generator circuit produces a scalable reference voltage with a number of diodes coupled to a source of a transistor that biases the diodes to establish a plurality of selectable reference voltages.

### Claim 5 (depends on 2)

The buffer of claim 2, wherein the second current limiting circuit further comprises a pass gate transistor coupled between the current limiting transistor and the reference voltage that passes the reference voltage to the source of the current limiting transistor based on a feedback signal from the output of the second inverter.

### Claim 6 (depends on 5)

The buffer of claim 5, wherein the second current limiting circuit further comprises a circuit that delays the feedback signal when turning off the pass gate transistor to improve the stability of the output of the buffer circuit.

### Claim 7

A buffer circuit, comprising:
a first inverter with a first current limiter that limits the standby current used by the first inverter:
a second inverter coupled to an output of the first inverter so as to convert a first logic level of an input signal provided to the first inverter to a second logic level at an output of the second inverter:
a second current limiting circuit coupled to an output of the first inverter and coupled to an input of the second inverter to further limit the standby current in the buffer; and
wherein the second current limiting circuit comprises first and second current limiting transistors, the first current limiting transistor coupled to the output of the first inverter to limit the standby current when a low logic level is applied to the first inverter and the second current limiting transistor coupled to the output of the first inverter to limit the standby current when a high logic level is applied to the first inverter.

### Claim 8

A memory device that is coupled to an electronic system, the memory device comprising:
a plurality of buffer circuits coupled to receive input signals from the electronic system, each buffer circuit including first and second inverters coupled to convert a first logic level of the input signal provided to the first inverter to a second logic level at an output of the second inverter, and a current limiting circuit coupled to an output of the first inverter and coupled to an input of the second inverter to limit the standby current in the buffer;
a control circuit that receives control signals from the electronic system through the buffer circuits to control the operation of the memory device;
an array of cells that store data for the electronic system;
an addressing circuit that receives address signals from the electronic system that identify a cell in the array of cells to be accessed by the electronic system; and
wherein the current limiting circuit comprises first and second transistors each having a gate coupled to receive the output signal of the second inverter such that the first transistor limits the standby current of the first inverter when the output of the buffer is a low logic level and the second transistor limits the standby current of the buffer when the output of the buffer is a high logic value.

### Claim 9

A memory device that is coupled to an electronic system, the memory device comprising:
a plurality of buffer circuits coupled to receive input signals from the electronic system, each buffer circuit including first and second inverters coupled to convert a first logic level of the input signal provided to the first inverter to a second logic level at an output of the second inverter, and a current limiting circuit coupled to an output of the first inverter and coupled to an input of the second inverter to limit the standby current in the buffer;
a control circuit that receives control signals from the electronic system through the buffer circuits to control the operation of the memory device;
an array of cells that store data for the electronic system;
an addressing circuit that receives address signals from the electronic system that identify a cell in the array of cells to be accessed by the electronic system; and
wherein the current limiting circuit comprises:
a current limiting transistor with a drain coupled to the output of the first inverter and the input of the second inverter in a standby current path for the buffer circuit; and
a reference voltage is coupled to the source of the current limiting transistor that establishes a low gate to source voltage for the transistor so as to limit the standby current.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the current limiting circuit further comprises a voltage generator circuit that a reference voltage that is approximately equal to a logic of the input signal.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the voltage generator circuit produces a scalable reference voltage with a number of diodes coupled to a source of a transistor that biases the diodes to establish a plurality of selectable reference voltages.

### Claim 12 (depends on 9)

The memory device of claim 9, wherein the current limiting circuit further comprises a pass gate transistor coupled between the current limiting transistor and the reference voltage that passes the reference voltage to the source of the current limiting transistor based on a feedback signal from the output of the second inverter.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the current limiting circuit further comprises a circuit that delays the feedback signal when mining off the pass gate transistor to improve the stability of the output of the buffer circuit.

### Claim 14

A memory device that is coupled to an electronic system, the memory device comprising:
a plurality of buffer circuits coupled to receive input signals from the electronic system, each buffer circuit including first and second inverters coupled to convert a first logic level of the input signal provided to the first inverter to a second logic level at an output of the second inverter, and a current limiting circuit coupled to an output of the first inverter and coupled to an input of the second inverter to limit the standby current in the buffer;
a control circuit that receives control signals from the electronic system through the buffer circuits to control the operation of the memory device;
an array of cells that store data for the electronic system;
an addressing circuit that receives address signals from the electronic system that identify a cell in the array of cells to be accessed by the electronic system; and
wherein the current limiting circuit comprises first and second current limiting transistors, the first current limiting transistor coupled to the output of the first inverter to limit the standby current when a low logic level is applied to the first inverter and the second current limiting transistor coupled to the output of the first inverter to limit the standby current when a high logic level is applied to the first inverter.

### Claim 15

A method for converting logic levels, comprising the steps of:
applying an input signal to a first inverter of a buffer circuit that inverts the input signal, the first inverter including a first current limiter that limits the standby current used by the first inverter;
applying the inverted input signal to a second inverter of the buffer circuit that is coupled to an output of the first inverter so as to convert a first logic level of the input signal provided to the first inverter to a second logic level at an output of the second inverter; and
limiting the standby current in the buffer circuit with a second current limiting circuit coupled to an output of the first inverter and coupled to an input of the second inverter, wherein the step of limiting the standby current comprises the step of limiting the standby current with first and second transistors, the first transistor coupled to limit the standby current when the input signal comprises a first logic level, and the second transistor coupled to limit the standby current when the input signal comprises a second logic level.