# US 5,703,495 A · Data output impedance control

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- Number: US 5,703,495 A
- Document ID: US5703495A
- Status: Granted
- Kind: A
- Application number: 08/421,586
- Filed: 1995-04-12
- Granted: 1997-12-30
- Earliest claimed: 1992-06-09
- Assignees: International Business Machines Corporation
- Inventors: Alfred Leonard Sartwell; Endre Philip Thoma
- Web page: https://patentgrep.com/patent/US5703495A

## CPC

- G01R 31/31701: {Arrangements for setting the Unit Under Test [UUT] in a test mode}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The present invention provides an apparatus and method for monitoring the functioning of a special operational mode on an integrated circuit module without the need for a special or dedicated pin. By monitoring the data output pins of the module operation in a special operational mode and premature interruption thereof, is detected. Delayed transition from a state of low impedance to a state of high impedance during the data output cycle is indicative of the special operational mode. The modules which usually have tri-state devices on their output lines are provided with delay circuitry to delay the transition of the tri-state device, during the data output cycle, from a state of low impedance to a state of high impedance while the device remains in a special operating mode.

## Claims

### Claim 1

A method of determining whether an integrated circuit module having an output control circuit is in a test mode, the output control circuit transitioning from a low impedance state to a high impedance state after a first time period during normal operation of the module, comprising the steps of:
maintaining a low impedance state of the output control circuit for a second time period greater than said first time period when the module is operated in a test mode; and
sampling data output of the module at a time falling between an end of the first time period and an end of the second time period to determine whether the output control circuit is in the low impedance state, thereby determining whether the module is in the test mode.

### Claim 2 (depends on 1)

The method of claim 1 further comprising the step of reverting to switching from the low impedance state to the high impedance state after said first time period if the test mode is prematurely interrupted.