# US 5,703,492 A · System and method for fault analysis of semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,492 A - Document ID: US5703492A - Status: Granted - Kind: A - Application number: 08/370,888 - Filed: 1995-01-10 - Granted: 1997-12-30 - Earliest claimed: 1994-01-10 - Assignees: NEC Corporation - Inventors: Toyokazu Nakamura; Yasuko Hanagama; Tohru Tsujide; Kenji Morohashi - Web page: https://patentgrep.com/patent/US5703492A ## CPC - G01R 31/31912: {Tester/user interface} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract In a fault analysis of large-scale integrated (LSI) circuits, a potential distribution image of a non-defective product and another potential distribution image of a defective product are displayed alternately and continuously in time, so that it is possible to acquire in real time an image of any location within a whole surface of the LSI chip. As a result, it can be viewed as if the potential distribution image of the non-defective product and the potential distribution image of the defective product are overlapped or superimposed with over time. Accordingly, a different portion between the non-defective and defective potential distribution images can be seen distinguishably from a coincident portion between the non-defective and defective potential distribution images, so that it is possible to trace the different portion in real time. ## Claims ### Claim 1 A fault analysis system for a semiconductor integrated circuit, for locating a fault portion in the semiconductor integrated circuit, comprising: means for continuously irradiating an electron beam on a semiconductor integrated circuit, means for detecting the amount of secondary electrons emitted from said semiconductor integrated circuit, means for applying a sequence of test patterns to said semiconductor integrated circuit, means for making a time of application of a selected test pattern to said semiconductor integrated circuit longer than that of other test patterns, means, coupled to said detecting means, for acquiring a potential circuit to be displayed in real-time, without being temporarily stored in a memory, picture by picture, and asynchronously with acquisition of said potential distribution image, and displaying alternately or simultaneously said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit in a same display or in different displays in real-time. ### Claim 2 (depends on 1) A fault analysis system claimed in claim 1 wherein said electron beam irradiating means continuously irradiates said electron beam. ### Claim 3 (depends on 1) A fault analysis system claimed in claim 1 further including means for calculating in real-time a difference in brightness between said potential distribution image for said non-defective condition and said potential distribution image for said defective condition, said calculating means causing a potential difference distribution image to be displayed on said displaying means in real-time. ### Claim 4 (depends on 1) A fault analysis system claimed in claim 1 further including means for standardizing the brightness of said potential distribution image for said non-defective condition and said potential distribution image for said defective condition, on the basis of a voltage supply voltage and a signal input voltage applied to the semiconductor integrated circuit in said non-defective condition and said defective condition. ### Claim 5 A fault analysis method for a semiconductor integrated circuit, for locating a fault portion in the semiconductor integrated circuit, said method comprising steps of: irradiating an electron beam on a semiconductor integrated circuit, detecting the amount of secondary electrons emitted from said semiconductor integrated circuit, applying a sequence of test patterns to a non-defective semiconductor integrated circuit and a defective semiconductor integrated circuit alternately or simultaneously, making a time of application of a selected test pattern to said semiconductor integrated circuit longer than that of other test patterns, acquiring a potential distribution image when said selected test pattern is applied to said non-defective semiconductor integrated circuit and said defective semiconductor integrated circuit, causing a potential distribution image for said non-defective semiconductor integrated circuit and said defective semiconductor integrated circuit to be displayed in real-time, and displaying alternately or simultaneously said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit in a same display or in different displays in real-time. ### Claim 6 (depends on 5) A fault analysis method claimed in claim 5, further comprising steps of calculating and displaying in real-time a difference in brightness between said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit. ### Claim 7 (depends on 5) A fault analysis method claimed in claim 5, further comprising steps of storing and judging respective locations of said non-defective semiconductor integrated circuit and said defective semiconductor integrated circuit. ### Claim 8 (depends on 5) A fault analysis method claimed in claim 5, further comprising steps of: locating said non-defective semiconductor integrated circuit and said defective semiconductor integrated circuit in a same chamber, and periodically moving said non-defective semiconductor integrated circuit and said defective semiconductor integrated circuit together with a frequency on an order of 0.5 Hz to 100 Hz, so that said non-defective semiconductor integrated circuit and said defective semiconductor integrated circuit are alternately positioned before said electron beam. ### Claim 9 (depends on 5) A fault analysis method claimed in claim 5, further comprising a step of: coloring said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit with different colors. ### Claim 10 (depends on 5) A fault analysis method claimed in claim 5, further comprising steps of: automatically defecting a deviation in position between said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit, and feeding back the detected deviation to an amount of displacement of said non-defective semiconductor integrated circuit or said defective semiconductor integrated circuit, so as to minimize the deviation in position between said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit when said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit are displayed on a same position. ### Claim 11 (depends on 5) A fault analysis method claimed in claim 5, further comprising steps of: detecting, by an operator, a deviation in position between said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit, and manually displacing the position of said non-defective semiconductor integrated circuit or said defective semiconductor integrated circuit, so as to minimize the deviation in position between said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit when said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit are displayed on a same position. ### Claim 12 (depends on 5) A fault analysis method claimed in claim 5, further comprising a step of: rotating a selected one of said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit around a selected point in said selected image when said potential distribution image for said non-defective semiconductor integrated circuit and said potential distribution image for said defective semiconductor integrated circuit are displayed on a same position. ### Claim 13 (depends on 1) A fault analysis system according to claim 1, wherein only a difference between said potential distribution image for a defective condition and said potential distribution image for a non-defective condition is on-and-off illuminated, said difference representing a defective portion of said product. ### Claim 14 (depends on 1) A fault analysis system according to claim 1, wherein only a difference between said potential distribution image for a defective condition and said potential distribution image for a non-defective condition is alternately emphasized on said means for displaying, such that a dynamic fault image is obtainable. ### Claim 15 (depends on 1) A fault analysis system according to claim 1, wherein a difference between a portion of said potential distribution image for said non-defective condition and a corresponding portion of said potential distribution image for said defective condition is made distinguishable on said means for displaying. ### Claim 16 (depends on 5) A fault analysis method according to claim 5, further comprising a step of on-and-off illuminating only a difference between said potential distribution image for said defective semiconductor integrated circuit and said potential distribution image for said non-defective semiconductor integrated circuit, such that a dynamic fault image is obtainable, said difference representing a defective portion of said semiconductor integrated circuit. ### Claim 17 (depends on 5) A fault analysis method according to claim 5, further comprising a step of alternately emphasizing only a difference between said potential distribution image for said defective semiconductor integrated circuit and said potential distribution image for said non-defective semiconductor integrated circuit. ### Claim 18 (depends on 1) A fault analysis system according to claim 1, wherein said means for displaying interactively displays said potential distribution images in real-time, such that when a region to be observed is changed, an alternate display can be subsequently obtained in the changed region to be observed. ### Claim 19 (depends on 1) A fault analysis system according to claim 1, wherein one said complete potential distribution image is acquired for a time period no greater than one second. ### Claim 20 (depends on 5) A fault analysis method according to claim 5, wherein said displaying step includes interactively displays said potential distribution images in real-time, such that when a region to be observed is changed, an alternate display can be subsequently obtained in the changed region to be observed. ### Claim 21 (depends on 5) A fault analysis method according to claim 5, wherein one said complete potential distribution image is acquired for a time period no greater than one second.