# US 5,703,405 A · Integrated circuit chip formed from processing two opposing surfaces of a wafer

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- Number: US 5,703,405 A
- Document ID: US5703405A
- Status: Granted
- Kind: A
- Application number: 08/591,194
- Filed: 1996-01-16
- Granted: 1997-12-30
- Earliest claimed: 1993-03-15
- Assignees: Motorola, Inc.
- Inventors: Kenneth Arthur Zeber
- Web page: https://patentgrep.com/patent/US5703405A

## CPC

- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/07236: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit chip (100) includes an integrated circuit die (105) having first and second opposing surfaces (110, 115). A first integrated circuit (205) is formed on the first surface (110), and has a first plurality of terminals (200) coupled thereto for connection to first circuitry external to the integrated circuit chip (100), wherein the first plurality of terminals (200) is formed on the first surface (110). A second integrated circuit (300) is formed on the second surface (115), is electrically isolated from the first integrated circuit (205), and has a second plurality of terminals (305) coupled thereto for connection to second circuitry external to the integrated circuit chip (100). The second plurality of terminals (305) is formed on the first surface (110) and is coupled to the second integrated circuit (300) via plated holes formed through the integrated circuit die (105). The second plurality of terminals (300) is electrically isolated from the first plurality of terminals (200) and the first integrated circuit (205).

## Claims

### Claim 1

An integrated circuit chip, comprising:
an integrated circuit die having first and second opposing surfaces;
a first integrated circuit formed on the first surface, the first integrated circuit having a first plurality of terminals coupled thereto for connection to first circuitry external to the integrated circuit chip, wherein the first plurality of terminals is formed on the first surface; and
a second integrated circuit formed on the second surface, the second integrated circuit electrically isolated from the first integrated circuit, the second integrated circuit having a second plurality of terminals coupled thereto for connection to second circuitry external to the integrated circuit chip, wherein the second plurality of terminals is formed on the first surface and coupled to the second integrated circuit via plated holes formed through the integrated circuit die, wherein the second plurality of terminals is electrically isolated from the first plurality of terminals and the first integrated circuit.

### Claim 2

An electronic assembly, comprising:
a circuit carrying substrate having first and second pluralities of contacts formed thereon; and
an integrated circuit chip mounted on the circuit carrying substrate, the integrated circuit chip comprising:
an integrated circuit die having first and second opposing surfaces;
a first integrated circuit formed on the first surface, the first integrated circuit having a first plurality of terminals coupled thereto for interconnection with the first plurality of contacts, wherein the first plurality of terminals is formed on the first surface; and
a second integrated circuit formed on the second surface, the second integrated circuit electrically isolated from the first integrated circuit, the second integrated circuit having a second plurality of terminals coupled thereto for interconnection with the second plurality of contacts, wherein the second plurality of terminals is formed on the first surface and coupled to the second integrated circuit via plated holes formed through the integrated circuit die, wherein the second plurality of terminals is electrically isolated from the first plurality of terminals and the first integrated circuit.

### Claim 3 (depends on 2)

The electronic assembly according to claim 2, wherein the first and second pluralities of terminals are coupled to the first and second pluralities of contacts utilizing flip-chip interconnect technology.

### Claim 4 (depends on 2)

The electronic assembly according to claim 2, wherein:
the integrated circuit chip is mounted on the circuit carrying substrate such that second surface of the integrated circuit die is adjacent to the circuit carrying substrate; and
a plurality of interconnects electrically couples the first and second pluralities of terminals to the first and second pluralities of contacts.

### Claim 5 (depends on 4)

The electronic assembly according to claim 4 wherein the first and second pluralities of terminals are coupled to the first and second pluralities of contacts utilizing wirebonding interconnect technology.

### Claim 6

An electronic device, comprising:
a circuit carrying substrate having first and second pluralities of contacts formed thereon;
circuitry for processing electrical signals mounted on the circuit carrying substrate, the circuitry including at least one integrated circuit chip comprising:
an integrated circuit die having first and second opposing surfaces;
a first integrated circuit formed on the first surface, the first integrated circuit having a first plurality of terminals coupled thereto for interconnection with the first plurality of contacts, wherein the first plurality of terminals is formed on the first surface; and
a second integrated circuit formed on the second surface, the second integrated circuit electrically isolated from the first integrated circuit, the second integrated circuit having a second plurality of terminals coupled thereto for interconnection with the second plurality of contacts, wherein the second plurality of terminals is formed on the first surface and coupled to the second integrated circuit via plated holes formed through the integrated circuit die, wherein the second plurality of terminals is electrically isolated from the first plurality of terminals and the first integrated circuit.

### Claim 7 (depends on 6)

The electronic device according to claim 6, wherein the circuitry comprises receiving circuitry for receiving and processing a radio frequency signal to recover therefrom a selective call message.

### Claim 8 (depends on 6)

The electronic device according to claim 6, wherein:
the integrated circuit chip is mounted on the circuit carrying substrate such that second surface of the integrated circuit die is adjacent to the circuit carrying substrate; and
a plurality of interconnects electrically couples the first and second pluralities of terminals to the first and second pluralities of contacts.

### Claim 9 (depends on 8)

The electronic device according to claim 8, wherein the first and second pluralities of terminals are coupled to the first and second pluralities of contacts utilizing wirebonding interconnect technology.