# US 5,703,392 A · Minimum size integrated circuit static memory cell

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- Number: US 5,703,392 A
- Document ID: US5703392A
- Status: Granted
- Kind: A
- Application number: 08/460,035
- Filed: 1995-06-02
- Granted: 1997-12-30
- Earliest claimed: 1995-06-02
- Inventors: Jeng-Jong Guo
- Web page: https://patentgrep.com/patent/US5703392A

## CPC

- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/12: {comprising a MOSFET load element}
- Y10S 257/903: FET configuration adapted for use as static memory cell
- Y10S 257/904: with passive components,, e.g. polysilicon resistors
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.

## Claims

### Claim 1

A semiconductor static memory cell comprising:
two cross-coupled inverters with a first inverter and a second inverter, each having a pull-up load device and a pull-down MOSFET with a drain, a source and a gate,
an output node of the first inverter of said cross-coupled inverters, where the drain of said pull-down MOSFET is connected to the load device, being coupled to the gate of the MOSFET of the second inverter of said cross-coupled inverters,
an output node of the second inverter of said cross-coupled inverters being coupled to the gate of the MOSFET of said first inverter,
a first MOSFET pass transistor having a gate connected to a word line, and two other electrodes, a source and a drain, connected between the output node of said first inverter and a bit line,
a second MOSFET pass transistor having a gate connected to said word line, and two other electrodes, a source and a drain, connected between the output node of said second inverter and a complementary bit line,
said first and second MOSFET pass transistors having a threshold voltage higher than said pull-down MOSFET, and
having a width-to-length ratio of the gate of the pull-down MOSFET less than 2.5 times the width-to-length ratio of the gate of the pass transistor.

### Claim 2 (depends on 1)

A semiconductor static memory cell as described in claim 1, wherein said load device is a MOSFET of complementary conductivity-type channel to said pull-down MOSFET with a gate connected to the gate of said pull-down MOSFET.

### Claim 3 (depends on 2)

A semiconductor static memory cell as described in claim 2, wherein the gate length and gate width of the pass transistor is the same as the gate length and gate width of the pull-down MOSFET respectively.

### Claim 4 (depends on 3)

A semiconductor static memory cell as described in claim 3, wherein said gate length and said gate width are of minimum dimension for a state-of-art processing technology.

### Claim 5 (depends on 1)

A semiconductor static memory cell as described in claim 1, wherein the threshold voltage of the pass transistor is increased by selectively implanting doping ions of same conductivity-type as the surface of the substrate of the pass transistor.

### Claim 6 (depends on 1)

A semiconductor static memory cell as described in claim 1, wherein the threshold voltage of the pull-down MOSFET is decreased by selectively implanting doping ions of opposite conductivity-type to the surface of the surface of the pull-down MOSFET.

### Claim 7 (depends on 1)

A semiconductor static memory cell as described in claim 1, wherein the threshold of the pass transistor is increased by making first gate oxide of the pass transistor thicker than second gate oxide of the pull-down MOSFET.

### Claim 8 (depends on 1)

A semiconductor static memory cell as described in claim 1, wherein the threshold voltage of the pass transistor is increased by doping the gate of the pass transistor differently from the doping of the gate of the pull-down transistor.

### Claim 9 (depends on 8)

A semiconductor static memory cell as described in claim 8, wherein the gate of the pass transistor is doped with p-type impurity and the gate of the pull-down transistor is doped with n-type impurity.

### Claim 10

A semiconductor static memory cell comprising:
two cross-coupled inverters, each having a pull-up load device and a pull-down MOSFET with a drain, a source and a gate,
an output node of the first inverter of said cross-coupled inverters, where the drain of said pull-down MOSFET is connected to the load device, being coupled to the gate of the MOSFET of the second inverter of said cross-coupled inverters,
a second output node of the second inverter of said cross-coupled inverters being coupled to the gate of the MOSFET of said first inverter,
a first MOSFET pass transistor having a gate connected to said word line, and two other electrodes, a source and a drain, connected between the output node of the said first inverter and a bit line,
a second MOSFET pass transistor having a gate connected to said word line, and two other electrodes, the source and the drain, connected between the output node of said second inverter and a complementary bit line,
said first and second MOSFET pass transistors having a lower transconductance parameter than the transconductance parameter of the pull-down MOSFET, and
said gate of said pull-down MOSFET having a ratio of width to length of said gate of said pull-down MOSFET less than 2.5 times the ratio of width to length of the gate of said pass transistor.

### Claim 11 (depends on 10)

A semiconductor static memory as claimed in claim 10, wherein, the adjustment of said conductance parameter is achieved by adjusting the thickness of the gate oxide of said first MOSFET pass transistor and said second MOSFET pass transistor.