# US 5,703,391 A · Semiconductor device having element isolating insulating film in contact hole

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- Number: US 5,703,391 A
- Document ID: US5703391A
- Status: Granted
- Kind: A
- Application number: 08/673,183
- Filed: 1996-06-27
- Granted: 1997-12-30
- Earliest claimed: 1996-06-27
- Assignees: Mitsubishi Denki Kabushiki Kaisha
- Inventors: Satoshi Arima
- Web page: https://patentgrep.com/patent/US5703391A

## CPC

- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10W 20/0698: {Local interconnections}
- Y10S 257/903: FET configuration adapted for use as static memory cell
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A semiconductor device is obtained which can suppress decrease in contact area between an interconnection layer and a semiconductor substrate. Further, a method of manufacturing a semiconductor device which can increase in contact resistance between first and second interconnection layers can be obtained. In the semiconductor device, upper surface of an element isolating insulating film is removed near a boundary point between the element isolating oxide film and the semiconductor substrate. Consequently, the surface of the semiconductor substrate is exposed where the element isolating insulating film has been removed. Since a conductive layer is formed to be in contact with the exposed semiconductor substrate, contact area between the conductive layer and the semiconductor substrate is increased. In the manufacturing method of the semiconductor device, foreign matters on the first interconnection layer derived from wet etching using hydrofluoric acid solution is removed by anisotropic dry etching, and thereafter a second interconnection layer is formed on the first interconnection layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having a main surface;
an element isolation insulating film formed on the main surface of said semiconductor substrate;
a conductive layer formed in contact with the main surface of said semiconductor substrate over a contact portion and in contact with a surface of said element isolation insulating film; wherein
at least an upper surface of said element isolating insulating film at a boundary point between said element isolating insulating film and said semiconductor substrate has been removed to form a concavity below the main surface of the semiconductor substrate which concavity forms part of the contact portion; and
said conductive layer is formed on contact with said semiconductor substrate and said element isolating insulating film positioned near said boundary point, wherein a step is formed at a region of the upper surface of said element isolating insulating film positioned below a side surface of said first interconnection layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
an impurity region of a first conductivity type is formed at the contact portion.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
said conductive layer includes
a first interconnection layer formed on the upper surface of said element isolating insulating film, and
a second interconnection layer formed in contact with said first interconnection layer, said element isolating insulating film and said semiconductor substrate.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a pair of source/drain regions of a first conductivity type formed spaced by a distance to define a channel region at the main surface of said semiconductor substrate, and
a gate electrode formed on said channel region with a gate insulating film interposed; wherein
one of said source/drain regions is formed continuous to said impurity region of the first conductivity type.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein
said conductive layer includes
a first interconnection layer formed on the upper surface of said element isolating insulating film, and
a second interconnection layer formed in contact with said first interconnection layer, said element isolating insulating film and said impurity region;
said gate electrode includes upper and lower layers; and
said first interconnection layer and the lower layer of said gate electrode are formed of one same layer, and said second interconnection layer and the upper layer of said gate electrode are formed of one same layer.