# US 5,703,389 A · Vertical IGFET configuration having low on-resistance and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,703,389 A - Document ID: US5703389A - Status: Granted - Kind: A - Application number: 08/393,772 - Filed: 1995-02-24 - Granted: 1997-12-30 - Earliest claimed: 1995-02-24 - Assignees: Motorola, Inc. - Inventors: Lynnita K. Knoch; Pak Tam - Web page: https://patentgrep.com/patent/US5703389A ## CPC - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/0293: {using formation of insulating sidewall spacers} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A vertical IGFET configuration includes a stripe arrangement having a non-linear shape. In one example, a stripe arrangement (30) has contact cut-out portions (41) and elongated portions (42). The elongated portions (42) have a width (44) that less than the width (43) of the contact cut-out portions (41). The stripe arrangement (30) increases channel density compared to typical individual cell configurations (10) and straight stripe configurations (20) thereby lowering on-resistance. ## Claims ### Claim 1 A vertical IGFET configuration having low on-resistance comprising a plurality of stripes formed on one surface of a semiconductor substrate and a drain electrode formed on an opposite surface of the semiconductor substrate, the plurality of stripes extending into the semiconductor substrate and having a non-linear shape that increases channel density thereby providing the low on-resistance, wherein each of the plurality of stripes includes a source region within a base region, and wherein the plurality of stripes is coupled together to form a single base configuration. ### Claim 2 (depends on 1) The configuration of claim 1 wherein the non-linear shape comprises contact cut-out portions having a first width and elongated portions having a second width less than the first width. ### Claim 3 An IGFET device having a plurality of stripe regions on one surface of a semiconductor substrate and a drain electrode on an opposite surface of the semiconductor substrate, comprising a configuration of the plurality of stripe regions to increase channel density, wherein each of the plurality of stripe regions has a pattern including elongated portions and contact cut-out portions, the contact cut-out portions wider than the elongated portions thereby increasing channel density, and wherein the plurality of stripe regions includes a plurality of source regions within a plurality of base regions, and wherein the plurality of base regions is coupled together to form a single base configuration. ### Claim 4 (depends on 3) The IGFET device of claim 3 wherein adjacent stripe regions are shifted such that the contact cut-out portions of one of the plurality of stripe regions are next to the elongated portions of an adjacent one of the plurality of stripe regions so that adjacent stripe regions are placed closer together thereby further increasing the channel density. ### Claim 5 (depends on 3) The IGFET device of claim 3 further comprising a plurality of doped contact regions, one within each of the contact cut-out portions, wherein the plurality of doped contact regions and the contact cut-out portions have a same shape. ### Claim 6 A vertical IGFET arrangement having low on-resistance comprising: a semiconductor substrate having a first surface and a second surface opposite the first surface; a plurality of well regions formed in the semiconductor substrate and extending from the first surface, each of the plurality of well regions having a non-linear stripe shape including a first portion having a first width and a second portion having a second width less than the first width and wherein each of the plurality of well regions is tied together to form a common base configuration; a source region formed within each of the plurality of well regions; a common drain electrode in contact with the second surface; and an insulated gate region formed between adjacent well regions. ### Claim 7 (depends on 6) The arrangement of claim 6 wherein adjacent well regions are offset such that the first portion of one of the plurality of well regions is next to a second portion of an adjacent one of the plurality of well regions. ### Claim 8 (depends on 7) The arrangement of claim 7 wherein a second portion of one of the plurality of well regions is spaced a distance in a range from 3.0 to 7.0 microns from a second portion of an adjacent one of the plurality of well regions. ### Claim 9 (depends on 8) The arrangement of claim 8 wherein the distance is in a range from 4.0 to 5.0 microns. ### Claim 10 (depends on 6) The arrangement of claim 6 wherein the second width is in a range from 1.0 to 3.5 microns. ### Claim 11 (depends on 10) The arrangement of claim 10 wherein the first width is approximately 0.5 to 2.0 microns greater than the second width. ### Claim 12 (depends on 6) The arrangement of claim 6 wherein the second portion has a height less than 20 microns. ### Claim 13 A method for forming a vertical IGFET device having low on-resistance comprising the steps of: providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a plurality of well regions in the semiconductor substrate extending from the first surface, each of the plurality of well regions having non-linear stripe shape, and wherein each of plurality of well regions is tied together to form a common base configuration; forming a source region within each of the plurality of well regions; forming an insulated gate region on the first surface; forming a source electrode in contact with the source region within each of the plurality of well regions; and forming a common drain electrode in contact with the second surface. ### Claim 14 (depends on 13) The method of claim 13 wherein the step of forming the plurality of well regions includes forming the plurality of well regions wherein each of the plurality of well regions has a stripe shape including a first portion having a first width and a second portion having a second width less than the first width. ### Claim 15 (depends on 14) The method of claim 14 wherein the step of forming the plurality of well regions includes forming a plurality of well regions wherein adjacent well regions are shifted such that the first portion of one of the plurality of well regions is next to the second portion of an adjacent one of the plurality of well regions. ### Claim 16 (depends on 14) The method of claim 14 wherein the step of forming the plurality of well regions includes forming a plurality of well regions wherein the second width is in a range from 1.0 to 3.5 microns, and wherein the first width is approximately 0.5 to 2.0 microns greater than the second width. ### Claim 17 (depends on 14) The method of claim 14 further comprising the step of forming a plurality of doped contact regions, one doped contact region within a first portion, wherein each of the plurality of doped contact regions and the first portion have a same shape.