# US 5,703,388 A · Double-poly monos flash EEPROM cell

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,703,388 A
- Document ID: US5703388A
- Status: Granted
- Kind: A
- Application number: 08/684,517
- Filed: 1996-07-19
- Granted: 1997-12-30
- Earliest claimed: 1996-07-19
- Assignees: Mosel Vitelic, Inc.
- Inventors: Chih-Hsien Wang; Min-Liang Chen; Thomas Chang
- Web page: https://patentgrep.com/patent/US5703388A

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/01346: {in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention discloses a double poly metal oxide.backslash.nitride.backslash.oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide.backslash.nitride.backslash.oxide layer, and a control gate. The control gate is formed on the oxide.backslash.nitride.backslash.oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.

## Claims

### Claim 1

A double-poly MONOS EEPROM formed on a semiconductor substrate, said EEPROM comprising:
a source formed in said substrate;
a drain formed in said substrate;
a gate oxide layer formed on said semiconductor substrate adjacent to said source and drain, said gate oxide layer being spaced apart from said drain by a first spacing width, said gate oxide layer being spaced apart from said source by a second spacing width;
a select gate formed on said gate oxide layer;
a dielectric layer formed on a portion of said select gate, a portion of said drain, and said first spacing width, said second spacing width being exposed by said select gate and said dielectric layer, said dielectric layer used to store carriers, said carriers tunneling into said dielectric layer via said first spacing width in a programming mode, wherein said select gate is used for conserving power in an erase mode; and
a control gate formed on said dielectric layer.

### Claim 2 (depends on 1)

The EEPROM of claim 1, wherein said dielectric layer is a triple composition layer that is comprised of oxide.backslash.nitride.backslash.oxide layers.

### Claim 3 (depends on 1)

The EEPROM of claim 1, wherein said select gate is formed of polysilicon.

### Claim 4 (depends on 1)

The EEPROM of claim 1, wherein said gate oxide layer is formed of silicon dioxide.

### Claim 5 (depends on 1)

The EEPROM of claim 1, wherein said control gate is formed of polysilicon.

### Claim 6 (depends on 1)

The EEPROM of claim 1 wherein said drain includes a lightly doped drain aligned with and under a portion of said control gate.