# US 5,702,986 A · Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,702,986 A - Document ID: US5702986A - Status: Granted - Kind: A - Application number: 08/567,692 - Filed: 1995-12-05 - Granted: 1997-12-30 - Earliest claimed: 1995-12-05 - Assignees: Micron Technology, Inc. - Inventors: Viju K. Mathews; Pierre C. Fazan; Nanseng Jeng - Web page: https://patentgrep.com/patent/US5702986A ## CPC - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10P 30/22: using masks - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract This invention is a process flow involving wordline spacer formation and source/drain implants which mitigates stress-induced damage to the silicon substrate during the post-implant anneal step. The process employs composite wordline spacers having a removable silicon dioxide portion and a non-removable silicon nitride portion. The post-implant anneal step is performed with only the silicon nitride portion of the spacer in place on the wordlines. The thinness of the silicon nitride portion greatly reduces the stress levels experienced by the substrate during the anneal as compared with that experienced by the substrate when thick one-piece silicon nitride spacers are left in place during the anneal. ## Claims ### Claim 1 A process for mitigating stress-induced damage to a silicon substrate during post-implant annealing of source/drain regions of a field-effect transistor, said transistor having a gate electrode which has been formed on the substrate, said electrode having sidewalls which are approximately normal to the substrate, said electrode also having an upper surface that is covered by an insulative layer, said process comprising the steps of: (a) depositing a conformal silicon nitride layer which covers the substrate, the sidewalls and the insulative layer; (b) depositing a conformal silicon dioxide layer which covers the conformal silicon nitride layer; (c) performing an anisotropic etch which forms spacers on each of the sidewalls, each spacer having both a silicon nitride portion and a silicon dioxide portion; (d) performing a source/drain implant with at least the silicon nitride portion of the spacer on the sidewalls; and (e) performing a post-implant anneal with only the silicon nitride portion of the spacer on the sidewalls. ### Claim 2 (depends on 1) The process of claim 1, wherein said conformal silicon nitride layer has a thickness that is less than half the thickness of said conformal silicon dioxide layer. ### Claim 3 (depends on 1) The process of claim 1, wherein said insulative layer comprises silicon nitride. ### Claim 4 (depends on 1) The process of claim 1, wherein said silicon nitride portion has an "L"-shaped cross-section. ### Claim 5 (depends on 1) The process of claim 1, wherein said at least one source/drain implant is performed with both portions of each spacer on the sidewalls. ### Claim 6 (depends on 1) The process of claim 1, wherein said post-implant anneal is performed at a temperature within a range of about 500.degree. C. to 1,000.degree. C. ### Claim 7 A process for forming an insulated-gate field-effect transistor on a silicon substrate, said process comprising the following steps: (a) growing a gate dielectric layer on the substrate; (b) depositing at least one conductive layer on top of the gate dielectric layer; (c) depositing an insulative layer on top of said at least one conductive layer; (d) forming a mask pattern on the insulative layer, said mask pattern having a profile which corresponds to that of a gate electrode; (e) anisotropically etching through both the insulative layer and the conductive layer to form a gate electrode having a insulative layer portion, a conductive layer portion and sidewalls formed from both the edges of the insulative layer portion and the conductive layer portion; (f) depositing a conformal silicon nitride layer which overlies the substrate and covers the sidewalls and the insulative layer portion; (g) depositing a conformal silicon dioxide layer which covers the conformal silicon nitride layer; (h) performing an anisotropic etch to form spacers from the silicon dioxide layer and the silicon nitride layer on each of the sidewalls, each spacer having both a silicon nitride portion and a silicon dioxide portion; (i) performing a source/drain implant with at least the silicon nitride portion of the spacer on the sidewalls; and (j) performing a post-implant anneal with only the silicon nitride portion of the spacer on the sidewalls. ### Claim 8 (depends on 7) The process of claim 7, which further comprises the step of performing an anti-punchthrough implant subsequent to step (e) and prior to step (f). ### Claim 9 (depends on 7) The process of claim 7, which further comprises the step of performing at least one source/drain implant subsequent to step (e) and prior to step (f). ### Claim 10 (depends on 7) The process of claim 7, wherein said conformal silicon nitride layer has a thickness that is less than half the thickness of said conformal silicon dioxide layer. ### Claim 11 (depends on 7) The process of claim 7, wherein said insulative layer comprises silicon nitride. ### Claim 12 (depends on 7) The process of claim 7, wherein said silicon nitride portion has an "L"-shaped cross-section. ### Claim 13 (depends on 9) The process of claim 9, wherein said at least one source/drain implant is performed with only the silicon nitride portion of each spacer on the sidewalls. ### Claim 14 (depends on 9) The process of claim 9, wherein said at least one source/drain implant is performed with both portions of each spacer on the sidewalls. ### Claim 15 (depends on 7) The process of claim 7, wherein said post-implant anneal is performed at a temperature within a range of about 500.degree. C. to 1,000.degree. C. ### Claim 16 A process for mitigating stress-induced damage to a silicon substrate during post-implant annealing of source/drain regions of a field-effect transistor, said transistor having a gate electrode which has been formed on the substrate, said electrode having sidewalls which are approximately normal to the substrate, said electrode also having an upper surface that is covered by an insulative layer, said process comprising the steps of: (a) depositing a conformal silicon nitride layer which covers the substrate, the sidewalls and the insulative layer; (b) depositing a conformal silicon dioxide layer which covers the conformal silicon nitride layer; (c) performing an anisotropic etch which forms spacers on each of the sidewalls, each spacer having both a silicon nitride portion and a silicon dioxide portion; (d) removing the silicon dioxide portion of each spacer; (e) performing a post-implant anneal with only the silicon nitride portion of the spacer on the sidewalls. ### Claim 17 (depends on 16) The process of claim 16, wherein a source/drain implant is performed subsequent to step (d) and prior to step (e). ### Claim 18 (depends on 16) The process of claim 16, wherein said conformal silicon nitride layer has a thickness that is less than half the thickness of said conformal silicon dioxide layer. ### Claim 19 (depends on 16) The process of claim 16, wherein said insulative layer comprises silicon nitride. ### Claim 20 (depends on 16) The process of claim 16, wherein said silicon nitride portion has an "L"-shaped cross-section.