Integrated mulitchip memory module, structure and fabrication

#The present invention relates in one aspect to high density electronic packaging which permits optimization of device performance within a given volume. In another aspect the invention relates to an integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by controlling logic such that a more powerful memory architecture having the functions of a single, higher level memory chip is presented to external circuitry.

#Conventionally, integrated circuit devices, such as memory devices, have been made from wafers of semiconductor material which include a plurality of integrated circuits. After a wafer is made, the circuits are separated from each other by dicing the wafer into small chips. Thereafter, the chips are bonded to carriers of various types, electrically interconnected by wires to leads and packaged.

#By way of improvement, high density electronic packaging modules having multiple semiconductor chips have become popular. For example, U.S. Pat. Nos. 4,525,921 and 4,646,128 by Carson et al. disclose structure and fabrication techniques for producing one type of high density electronic processing package. Each of these patents describes a semiconductor chip stack consisting of multiple integrated circuit chips adhesively secured together. A metallized pattern is provided on one of the side surfaces of the stack for electrical connection of the stack to external circuitry. This metallization pattern typically includes both individual contacts and bused contacts. The stack is positioned on an upper surface of a substrate such that electrical contact is made between the stack metallization pattern and a substrate surface metallization pattern.

#These and other objects, advantages and features of the present invention will be more readily understood from the following detailed description of certain preferred embodiments of the present invention, when considered in conjunction with the accompanying drawings in which:

#FIG. 1 is a perspective view of one embodiment of an integrated multichip memory module pursuant to the present invention;

#FIG. 2 is a cross-sectional elevational view of the integrated multichip memory module of FIG. 1 taken along lines 2--2;

#An integrated multichip memory module in accordance with the invention can be implemented using any one of a variety of available memory chip architectures. By way of example, the following discussion assumes that four 16 Mb DRAMs are to be assembled in a memory stack. This multichip memory module emulates exactly a next generation memory chip, i.e., a 64 Mb DRAM. This integrated, function is accomplished by associating a control logic chip with the stack of four memory chips. The resultant module of four 16 Mb DRAMs plus logic chip can be sized to fit into an industry standard 64 Mb package, or if desired, a smaller package. Compared with single memory chips, there are significant processing, manufacturability and cost advantages to this integrated multichip memory module structure in accordance with this invention.

#In the figures, which are not drawn to scale for ease of understanding, the same reference numbers are throughout multiple figures to designate the same or similar components. FIG. 1 depicts one embodiment of the integrated multichip memory module, generally denoted 10, pursuant to the invention. In this embodiment, four memory chips (M) 14 are connected in a stack 12 having the shape of a rectangular parallelepiped. Each memory chip 14 has two substantially parallel planar main surfaces and an edge surface with at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip in the stack 12. Multiple layers 16 (see FIG. 5) are disposed between adjacent memory chips 14. Each layer 16 contains appropriate transfer metallurgy 15 (FIG. 2) and insulation layers 17A to provide electrical connection to the storage devices of the respective memory chip. An adhesive layer 17 (FIG. 5) such as a Thermid.RTM. polymer (TM of National Starch and Chemical Co.) secures adjacent memory chips 14 together. Disposed along at least one end surface of stack 12 is a preformed electrical interface layer 18 which has a metallization pattern 28 therethrough.

#In one embodiment, layer 18 comprises a Upilex (or alternative insulator) flex layer wherein plated throughholes or vias interconnect some thin-film wiring on a top surface of layer 18 and thin-film wiring on a bottom surface of the layer (see, e.g., FIG. 2). (There is other top surface thin-film wiring 25B which provides for the interconnection of the logic chip 22 and lead frame 32.) Together these wirings comprise metallization pattern 28, only one thin-film wire is shown in phantom in FIG. 1. The metallization pattern within electrical interface layer 18 routes, for example, 16 Mb wiring from a control logic chip 22 to another metallization pattern 20 disposed on an insulator 21 on at least one side surface of stack 12. Only one type of metallization pattern 20 is depicted in FIG. 1 for clarity. T connects are employed at the interface between metallization pattern 28 and metallization pattern 20. If desired, multiple side surfaces of stack 12 could accommodate buses or other wiring connections to the semiconductor memory chips (M). Standard transfer metallurgy 15 is brought out and electrically connected to metallization pattern 20 on the at least one side surface of stack 12. Again, interconnection of transfer metallurgy 15 and metallization pattern 20 is achieved using T-connects.