# US 5,702,983 A · Method for manufacturing a semiconductor device with a metallic interconnection layer

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- Number: US 5,702,983 A
- Document ID: US5702983A
- Status: Granted
- Kind: A
- Application number: 08/671,952
- Filed: 1996-06-28
- Granted: 1997-12-30
- Earliest claimed: 1993-11-02
- Assignees: Sony Corporation
- Inventors: Kenji Shinohara
- Web page: https://patentgrep.com/patent/US5702983A

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device having a metallic interconnection layer is described. The method includes the steps of providing a substrate having an insulating film, forming at least one contact hole in the insulating film, forming a first metallic interconnection layer on the insulating film so that the contact hole is filled with the interconnection layer, and forming a second metallic interconnection layer on the first layer to provide a builtup structure. The second layer may be formed by a high temperature sputtering method wherein a substrate temperature is 400.degree. C. or over or by a procedure which includes forming a second metallic interconnection layer by an ordinary sputtering method and heating the substrate to a temperature not lower than 450.degree. C. to cause the second layer to be reflown. By this, the second has a smooth surface irrespective of the presence of irregularities on the surface of the first layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor device with a built-up metallic interconnection layer comprising the steps of:
providing a substrate with a surface;
forming an insulating layer on the surface;
forming a contact hole having a diameter in the insulating layer to expose a selected portion of the substrate;
forming a first bonding layer on the insulating layer and contact hole;
forming a tungsten interconnection layer on the first bonding layer having a thickness not less than 50% of the diameter of the contact hole and completely filling the contact hole;
forming a second bonding layer on the tungsten interconnection layer without etching back the tungsten interconnection layer;
forming a metallic interconnection layer selected from aluminum and alloys of aluminum with at least one of Si, Cu and Ti on the second bonding layer to form a built-up interconnection layer; and
subjecting the built-up interconnection layer to elevated temperatures of from about 400.degree. C. to about 500.degree. C. under a reduced pressure less than atmospheric pressure for a time sufficient to reflow the metallic interconnection layer without melting the metallic interconnection layer to provide a built-up interconnection layer having a smooth surface.

### Claim 2 (depends on 1)

A method according to claim 1, wherein said temperature is within a range of from 450.degree. C. to 500.degree. C.

### Claim 3 (depends on 1)

A method according to claim 1, wherein said tungsten interconnection layer is formed by a CVD method.

### Claim 4 (depends on 1)

A method according to claim 1, wherein said first and second bonding layers include a single layer or a plurality of layers made of a Ti material.

### Claim 5 (depends on 1)

A method according to claim 1, wherein said second bonding layer is selected from the group consisting of Ti, TiON, TiN and TiW.

### Claim 6 (depends on 1)

A method as defined in claim 1, wherein the subjecting step is performed during the forming of the metallic interconnection layer.