# US 5,702,977 A · Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer

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- Number: US 5,702,977 A
- Document ID: US5702977A
- Status: Granted
- Kind: A
- Application number: 08/810,390
- Filed: 1997-03-03
- Granted: 1997-12-30
- Earliest claimed: 1997-03-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Syun-Ming Jang; Ying-Ho Chen; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US5702977A

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- Y10S 148/05: Etch and refill
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer. The trench fill layer is formed to a thickness over the trench such that when the trench fill layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill layer formed within the trench.

## Claims

### Claim 1

A method for forming and planarizing a trench fill layer within a trench within an integrated circuit comprising:
providing a substrate, the substrate having a trench formed therein;
forming upon the substrate at regions other than those within the trench a first integrated circuit layer, the first integrated circuit layer having a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench;
forming within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer, the second integrated circuit layer having a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench; and
forming upon the substrate and within the trench the trench fill layer, the trench fill layer being formed to a thickness over the trench such that when the trench fill layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill layer formed within the trench.

### Claim 2 (depends on 1)

The method of claim 1 wherein the substrate is selected from the group of substrates consisting of dielectric substrates, semiconductor substrates and conductor substrates.

### Claim 3 (depends on 1)

The method of claim 1 wherein the trench has a width greater than about 0.3 microns.

### Claim 4 (depends on 1)

The method of claim 1 wherein the trench fill layer is a silicon oxide trench fill layer formed through an ozone assisted thermal chemical vapor deposition (CVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1 and a reactor chamber pressure of from about 450 to about 600 torr (without plasma activation).

### Claim 5 (depends on 4)

The method of claim 4 wherein the first integrated circuit layer is a silicon oxide insulator layer formed through a thermal oxidation method.

### Claim 6 (depends on 4)

The method of claim 4 wherein the second integrated circuit layer is a silicon oxide insulator layer formed through a thermal oxidation method and subsequently treated with a nitrogen plasma.

### Claim 7 (depends on 6)

The method of claim 6 wherein the nitrogen plasma is employed at:
a reactor chamber pressure of from about 1 to about 2 torr;
a mixed frequency radio frequency power of about 75 to about 125 watts at a radio frequency of 13.56 MHZ and about 400 to about 500 watts at a radio frequency of 350 kHz; and
an exposure time of from about 50 to about 70 seconds.

### Claim 8 (depends on 4)

The method of claim 4 wherein the second integrated circuit layer is a silicon oxide insulator layer formed through an ozone assisted thermal chemical vapor deposition (CVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material at an ozone:TEOS volume ratio of about 2:1 to about 4:1 and a reactor chamber pressure of from about 40 to about 70 torr (without plasma activation).

### Claim 9 (depends on 4)

The method of claim 4 wherein the second integrated circuit layer is a silicon oxide integrated circuit layer formed through a plasma enhanced chemical vapor deposition (PECVD) employing silane as a silicon source material.

### Claim 10 (depends on 9)

The method of claim 9 wherein the plasma enhanced chemical vapor deposition method also employs a nitrous oxide oxidant and a radio frequency power of from about 160 to about 240 watts at a radio frequency of 13.56 MHZ.

### Claim 11

A method for forming and planarizing a trench fill dielectric layer within an isolation trench within an integrated circuit comprising:
providing a substrate, the substrate having an isolation trench formed therein;
forming upon the substrate at regions other than those within the isolation trench a first integrated circuit layer, the first integrated circuit layer having a composition which inhibits formation upon the first integrated circuit layer of a trench fill dielectric layer which is subsequently formed upon the substrate and within the isolation trench;
forming within the isolation trench but not upon the substrate at regions other than those within the isolation trench a second integrated circuit layer, the second integrated circuit layer having a composition which promotes formation within the isolation trench of the trench fill dielectric layer which is subsequently formed upon the substrate and within the isolation trench; and
forming upon the substrate and within the isolation trench the trench fill dielectric layer, the trench fill dielectric layer being formed to a thickness over the isolation trench such that when the trench fill dielectric layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill dielectric layer formed within the isolation trench.

### Claim 12 (depends on 11)

The method of claim 11 wherein the substrate is a semiconductor substrate.

### Claim 13 (depends on 11)

The method of claim 11 wherein the isolation trench has a width greater than about 0.3 microns.

### Claim 14 (depends on 11)

The method of claim 11 wherein the trench fill dielectric layer is a silicon oxide trench fill dielectric layer formed through an ozone assisted thermal chemical vapor deposition (CVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1 and a reactor chamber pressure of from about 450 to about 600 torr (without plasma activation).

### Claim 15 (depends on 14)

The method of claim 14 wherein the first integrated circuit layer is a silicon oxide insulator layer formed through a thermal oxidation method.

### Claim 16 (depends on 14)

The method of claim 14 wherein the second integrated circuit layer is a silicon oxide insulator layer formed through a thermal oxidation method and subsequently treated with a nitrogen plasma.

### Claim 17 (depends on 16)

The method of claim 16 wherein the nitrogen plasma is employed at:
a reactor chamber pressure of from about 1 to about 2 torr;
a mixed frequency radio frequency power of about 75 to about 125 watts at a radio frequency of 13.56 MHZ and about 400 to about 500 watts at a radio frequency of 350 kHz; and
an exposure time of from about 50 to about 70 seconds.

### Claim 18 (depends on 14)

The method of claim 14 wherein the second integrated circuit layer is a silicon oxide insulator layer formed through an ozone assisted thermal chemical vapor deposition (CVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material at an ozone:TEOS volume ratio of about 2:1 to about 4:1 and a reactor chamber pressure of from about 40 to about 70 torr (without plasma activation).

### Claim 19 (depends on 14)

The method of claim 14 wherein the second integrated circuit layer is a silicon oxide integrated circuit layer formed through a plasma enhanced chemical vapor deposition (PECVD) employing silane as a silicon source material.

### Claim 20 (depends on 19)

The method of claim 19 wherein the plasma enhanced chemical vapor deposition method also employs a nitrous oxide oxidant and a radio frequency power of from about 160 to about 240 watts at a radio frequency of 13.56 MHZ.