# US 5,702,976 A · Shallow trench isolation using low dielectric constant insulator

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- Number: US 5,702,976 A
- Document ID: US5702976A
- Status: Granted
- Kind: A
- Application number: 08/547,620
- Filed: 1995-10-24
- Granted: 1997-12-30
- Earliest claimed: 1995-10-24
- Assignees: Micron Technology, Inc.
- Inventors: Klaus F. Schuegraf; Aftab Ahmad
- Web page: https://patentgrep.com/patent/US5702976A

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- Y10S 148/05: Etch and refill
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced wench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

## Claims

### Claim 1

A process for isolating devices on a semiconductor substrate comprising the steps of:
removing predetermined portions of the semiconductor substrate forming recesses therein; and
refilling the portions of the semiconductor substrate with a material comprising an in situ doped silicon oxide complex, the material having a dielectric constant lower than the dielectric constant of undoped silicon dioxide.

### Claim 2 (depends on 1)

The process of claim 1, wherein the step of removing portions of the semiconductor wafer comprises forming trenches in the semiconductor wafer.

### Claim 3 (depends on 2)

The process of claim 2, wherein the trenches have a depth of less than 200 nm.

### Claim 4 (depends on 3)

The process of claim 3, wherein the trenches have an aspect ratio of less than 2:1.

### Claim 5

A process for isolating devices on a semiconductor substrate comprising the steps of:
removing predetermined portions of the semiconductor substrate forming recesses therein; and
refilling the portions of the semiconductor substrate with a material having a dielectric constant lower than the dielectric constant of silicon dioxide,
wherein the material having a dielectric constant lower than that of silicon dioxide comprises a halide-doped silicon dioxide composition.

### Claim 6 (depends on 5)

The process of claim 5, wherein the halide-doped silicon dioxide complex comprises a Fluorine-doped silicon dioxide complex.

### Claim 7 (depends on 1)

The process of claim 1, wherein the refilling material has a dielectric constant less than about 3.9.

### Claim 8 (depends on 1)

The process of claim 1, further comprising forming a barrier layer over the semiconductor substrate prior to the step of refilling portions of the semiconductor substrate.

### Claim 9 (depends on 8)

The process of claim 8, wherein the barrier layer comprises a silicon dioxide composition.

### Claim 10 (depends on 8)

The process of claim 8, wherein the barrier layer comprises a silicon nitride composition.

### Claim 11

A method of reducing the formation of voids in a refilled trench isolation process comprising the steps of:
forming trenches having an aspect ratio less than 2:1;
refilling the trenches with an insulating material; and
halide-doping the material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the trenches have a depth of less than 200 nm.

### Claim 13

A method of reducing the formation of voids in a refilled trench isolation process comprising the steps of:
forming trenches having an aspect ratio less than 2:1; and
refilling the trenches with a material having a dielectric constant less than the dielectric constant of silicon dioxide,
wherein the refilling material comprises a Fluorine-doped silicon dioxide composition.

### Claim 14 (depends on 11)

The method of claim 11, wherein the halide-doped material has a dielectric constant of less than about 3.9.

### Claim 15 (depends on 1)

The method of claim 1, wherein the material comprises a halide-doped oxide.

### Claim 16 (depends on 1)

The method of claim 1, wherein the material comprises a fluoride-doped oxide.

### Claim 17 (depends on 11)

The method of claim 11, wherein refilling the trenches comprises depositing silicon dioxide.

### Claim 18 (depends on 17)

The method of claim 17, wherein depositing silicon dioxide comprises a chemical vapor deposition.

### Claim 19 (depends on 18)

The method of claim 18, wherein halide-doping the material comprises in situ halide doping during chemical vapor deposition of the material.

### Claim 20 (depends on 11)

The method of claim 11, wherein doping the material comprises introducing a halide into the material while refilling the trenches.

### Claim 21 (depends on 11)

The method of claim 11, wherein the halide comprises fluorine.

### Claim 22

A process for isolating devices on a semiconductor substrate comprising the steps of:
forming trenches within the substrate;
lining the trenches with a diffusion barrier;
refilling the trenches with silicon dioxide; and
halide-doping silicon dioxide.
