# US 5,702,972 A · Method of fabricating MOSFET devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,702,972 A - Document ID: US5702972A - Status: Granted - Kind: A - Application number: 08/789,716 - Filed: 1997-01-27 - Granted: 1997-12-30 - Earliest claimed: 1997-01-27 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chaochieh Tsai; Shun-Liang Hsu; Shaulin Shue - Web page: https://patentgrep.com/patent/US5702972A ## CPC - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 30/0212: {using self-aligned silicidation} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 64/0112: {using conductive layers comprising silicides} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs} - H10D 84/0137: {the gate conductors being silicided} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method for improving the source/drain resistance in the fabrication of an integrated circuit device is described. Gate electrodes are formed on the surface of a semiconductor substrate. Lightly doped regions are implanted into the semiconductor substrate using the gate electrodes as a mask. First spacers are formed on the sidewalls of the gate electrodes. Second spacers are formed on the sidewalls of the first spacers. Heavily doped source and drain regions are implanted into the semiconductor substrate using the gate electrodes and first and second spacers as a mask. Thereafter, the second spacers are removed. A titanium layer is deposited by chemical vapor deposition over the substrate whereby titanium silicide is formed overlying the gate electrodes and overlying the source and drain regions and whereby elemental titanium is deposited overlying the first spacers wherein the titanium silicide overlying the source and drain regions improves the source/drain resistance. The elemental titanium is removed. The substrate is annealed to transform all of the silicide into C54-phase TiSi.sub.2 and the fabrication of the integrated circuit device is completed. ## Claims ### Claim 1 A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; forming first insulating spacers on the sidewalls of said gate electrodes; forming second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby titanium silicide is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers wherein said titanium silicide overlying said source and drain regions reduces said source and drain resistance; removing said elemental titanium; and completing the fabrication of said integrated circuit device, including the step of depositing an insulating layer overlying said gate electrodes and said titanium silicide. ### Claim 2 (depends on 1) The method according to claim 1 wherein said gate electrodes are composed of polysilicon. ### Claim 3 (depends on 1) The method according to claim 1 wherein said first spacers are formed by growing a thermal oxide layer on the sidewalls of said gate electrodes to a thickness of between about 100 and 300 Angstroms. ### Claim 4 (depends on 1) The method according to claim 1 wherein said second spacers are formed by depositing a layer of silicon nitride over the surface of said substrate and anisotropically etching away said silicon nitride layer to leave said silicon nitride layer as said second spacers on said sidewalls of said first spacers wherein said second spacers have a thickness of between about 1000 and 1500 Angstroms. ### Claim 5 (depends on 1) The method according to claim 1 wherein said depositing said titanium layer is done at a temperature of between about 400.degree. and 700.degree. C. to a thickness of between about 100 and 400 Angstroms. ### Claim 6 (depends on 1) The method according to claim 1 wherein said titanium silicide as deposited comprises C49-TiSi.sub.2 and further comprising annealing said substrate to transform said titanium silicide to C54-TiSi.sub.2 after said removing said elemental titanium. ### Claim 7 (depends on 1) The method according to claim 1 wherein the space between said gate electrodes is as small as 0.13 to 0.35 micron. ### Claim 8 (depends on 1) The method according to claim 1 wherein the junction depth of said source and drain regions is between about 1500 and 2000 Angstroms. ### Claim 9 A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; forming first insulating spacers on the sidewalls of said gate electrodes; forming second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby titanium silicide is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers wherein said titanium silicide overlying said source and drain regions reduces said source and drain resistance; removing said elemental titanium; annealing said substrate to transform said titanium silicide from C49 phase to C54 phase titanium silicide; depositing an insulating layer overlying said gate electrodes and said titanium silicide; etching contact openings through said insulating layer to said underlying gate electrodes and source and drain regions; and filling said contact openings with a conducting layer and patterning said conducting layer to complete the fabrication of said integrated circuit device. ### Claim 10 (depends on 9) The method according to claim 9 wherein said gate electrodes are composed of polysilicon. ### Claim 11 (depends on 9) The method according to claim 9 wherein said first spacers are formed by growing a thermal oxide layer on the sidewalls of said gate electrodes to a thickness of between about 100 and 300 Angstroms. ### Claim 12 (depends on 9) The method according to claim 9 wherein said second spacers are formed by depositing a layer of silicon nitride over the surface of said substrate and anisotropically etching away said silicon nitride layer to leave said silicon nitride layer as said second spacers on said sidewalls of said first spacers wherein said second spacers have a thickness of between about 1000 and 1500 Angstroms. ### Claim 13 (depends on 9) The method according to claim 9 wherein said depositing said titanium layer is done at a temperature of between about 400.degree. and 700.degree. C. to a thickness of between about 100 and 400 Angstroms. ### Claim 14 (depends on 9) The method according to claim 9 wherein said titanium silicide as deposited comprises C49-TiSi.sub.2 and wherein said annealing at a temperature of between about 800.degree. and 900.degree. C. transforms said titanium silicide to C54-TiSi.sub.2. ### Claim 15 (depends on 9) The method according to claim 9 wherein the space between said gate electrodes is as small as 0.13 to 0.35 micron. ### Claim 16 (depends on 1) The method according to claim 1 wherein the junction depth of said source and drain regions is between about 1500 and 2000 Angstroms. ### Claim 17 A method of reducing source and drain resistance in the fabrication of an integrated circuit device comprising the steps of: providing polysilicon gate electrodes on the surface of a semiconductor substrate; implanting lightly doped regions into said semiconductor substrate using said gate electrodes as a mask; growing first thermal oxide insulating spacers on the sidewalls of said gate electrodes; depositing a layer of silicon nitride over the surface of said substrate and anisotropically etching to leave said silicon nitride layer as second insulating spacers on the sidewalls of said first spacers; implanting heavily doped source and drain regions into said semiconductor substrate using said gate electrodes and said first and second spacers as a mask; thereafter removing said second spacers; depositing by chemical vapor deposition a titanium layer over said substrate whereby C49-TiSi.sub.2 is formed overlying said gate electrodes and overlying said source and drain regions and whereby elemental titanium is deposited overlying said first spacers; removing said elemental titanium; annealing said substrate to transform said C49-TiSi.sub.2 into C54-TiSi.sub.2 wherein said C54-TiSi.sub.2 overlying said source and drain regions reduces said source and drain resistance; depositing an insulating layer overlying said gate electrodes and said C54-TiSi.sub.2 ; etching contact openings through said insulating layer to said underlying gate electrodes and source and drain regions; and filling said contact openings with a conducting layer and patterning said conducting layer to complete the fabrication of said integrated circuit device. ### Claim 18 (depends on 17) The method according to claim 17 wherein said first spacers have a thickness of between about 100 and 300 Angstroms. ### Claim 19 (depends on 17) The method according to claim 17 wherein said second spacers have a thickness of between about 1000 and 1500 Angstroms. ### Claim 20 (depends on 17) The method according to claim 17 wherein the space between said gate electrodes is as small as 0.13 to 0.35 micron.