# US 5,702,969 A · Buried bit line DRAM cells and fabricating methods therefor

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- Number: US 5,702,969 A
- Document ID: US5702969A
- Status: Granted
- Kind: A
- Application number: 08/637,223
- Filed: 1996-04-24
- Granted: 1997-12-30
- Earliest claimed: 1995-04-25
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Kang-yoon Lee
- Web page: https://patentgrep.com/patent/US5702969A

## CPC

- H10W 20/021: {of interconnections within wafers or substrates}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- Y10S 257/908: Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A buried bit line DRAM cell includes an active region having a protruding tap, formed in a semiconductor substrate. A device isolation region is formed in the substrate, outside the active region. A bit line laterally contacts the tap and is buried in the device isolation region. Accordingly, photolithography steps for forming a device isolation film twice and for forming a bit line contact can be omitted, thereby obtaining process simplicity and wider process margins.

## Claims

### Claim 1

A method of fabricating an integrated circuit dynamic random access memory (DRAM) cell, comprising the steps of:
forming a DRAM cell active region in a substrate, said DRAM cell active region including a protruding tap extending therefrom;
forming a device isolation region in said substrate, outside said DRAM cell active region; and
forming a buried bit line in said device isolation region, which projects through said device isolation region to electrically contact said tap.

### Claim 2 (depends on 1)

A method according to claim 1 wherein said step of forming a DRAM cell active region comprises the step of forming a DRAM cell active region which extends along said substrate in a first direction and a protruding tap which extends along said substrate in a second direction which is orthogonal to said first direction, and wherein said step of forming a buried bit line comprises the step of forming a buried bit line which extends along said substrate in said first direction.

### Claim 3

A method of fabricating an integrated circuit dynamic random access memory (DRAM) cell, comprising the steps of:
etching a semiconductor substrate to thereby define a DRAM cell active region in said substrate, including a protruding tap extending therefrom, and a trench in said semiconductor substrate which surrounds said DRAM cell active region including said protruding tap, said trench including a trench sidewall;
forming a device isolation film on said trench sidewall, said device isolation film exposing said tap; and
forming a conductor in said trench, such that said conductor electrically contacts said tap but is electrically insulated from said DRAM cell active region outside said tap.

### Claim 4 (depends on 3)

A method according to claim 3 wherein said etching step comprises the step of etching a semiconductor substrate to thereby define a DRAM cell active device region which extends along said substrate in a first direction and a protruding tap which extends along said substrate in a second direction which is orthogonal to said first direction, and wherein said step of forming a conductor comprises the step of forming a conductor in said trench which extends along said substrate in said first direction.

### Claim 5

A method of fabricating an integrated circuit dynamic random access memory (DRAM) cell, comprising the steps of:
etching a semiconductor substrate to thereby define a DRAM cell active region in said semiconductor substrate, including a protruding tap extending therefrom, and a first trench in said semiconductor substrate which surrounds said DRAM cell active region including said protruding tap;
filling said first trench with insulating material;
forming a second trench in said insulating material, such that said second trench exposes said tap; and
filling said second trench with conductive material to thereby form a bit line which electrically contacts said tap.

### Claim 6 (depends on 5)

A method according to claim 5 wherein said step of filling said second trench is followed by the step of forming insulating material on said bit line.

### Claim 7 (depends on 5)

A method according to claim 5 wherein said step of filling said first trench comprises the steps of:
blanket depositing insulating material on said semiconductor substrate including said first trench; and
removing said insulating material from said semiconductor substrate outside said first trench.

### Claim 8 (depends on 7)

A method according to claim 7 wherein said removing step comprises the step of chemical mechanical polishing said semiconductor substrate.

### Claim 9 (depends on 5)

A method according to claim 5 wherein said step of filling said second trench comprises the steps of:
blanket depositing conductive material on said semiconductor substrate including said second trench; and
removing said conductive material from said semiconductor substrate outside said second trench.

### Claim 10 (depends on 5)

A method according to claim 5 wherein said step of filling said second trench comprises the step of filling said second trench with conductive material selected from the group consisting of polysilicon, metal, silicide and polycide.

### Claim 11 (depends on 5)

A method according to claim 5 wherein the following step is performed between said steps of forming a second trench and filling said second trench:
implanting ions into said tap through the exposed portion of said second trench.

### Claim 12 (depends on 6)

A method according to claim 6 wherein said step of forming insulating material on said bit line comprises the steps of:
blanket depositing insulating material on said semiconductor substrate including said bit line; and
removing said insulating material from said semiconductor substrate outside said bit line.