A method of fabricating a deep, submicron MOSFET device, on a semiconductor substrate, with a narrow polysilicon gate structure, self aligned to a local threshold voltage adjust region, comprising the steps of:
- depositing a first insulator layer on said semiconductor substrate;
- forming a photoresist pattern on said first insulator layer, with a deep submicron opening in said photoresist pattern, exposing top surface of said first insulator layer;
- forming a deep submicron hole opening, in said first insulator layer, by removing said first insulator layer, from an area defined by said deep submicron opening in said photoresist pattern;
- thermal oxidation to grow a second insulator layer, to be used as a gate insulator layer, on the surface of said semiconductor substrate, exposed in said deep submicron hole opening;
- ion implanting a first conductivity imparting dopant through said second insulator layer, and into an area of said semiconductor substrate, defined by said deep submicron hole opening, to create said local threshold voltage adjust region;
- depositing a polysilicon layer, on top surface of said first insulator layer, and completely filling said deep submicron hole opening;
- oxidation to convert said polysilicon layer, on top surface of said first insulator layer, to a silicon oxide layer, while converting a top portion of said polysilicon layer, in said deep submicron hole opening, to said silicon oxide layer, leaving bottom portion of said polysilicon layer, in said deep submicron hole opening, unoxidized, and forming said narrow polysilicon gate structure, recessed in said deep submicron hole opening, self aligned to underlying, said narrow local threshold voltage adjust region;
- removal of said silicon oxide layer, from top surface of said first insulator layer, and from top surface of said narrow polysilicon gate structure, recessed in said deep submicron hole opening;
- removal of said first insulator layer;
- ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said narrow polysilicon gate structure, to form a lightly doped source and drain region;
- depositing a third insulator layer on said semiconductor substrate, and on said narrow polysilicon gate structure;
- anisotropic etching of said third insulator layer to form an insulator spacer on the sides of said narrow polysilicon gate structure;
- ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said narrow polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region;
- depositing a fourth insulator layer on said semiconductor substrate, and on said narrow polysilicon gate structure;
- opening a contact hole in said fourth insulator layer, to expose top surface of said heavily doped source and drain regions, and to expose top surface of said narrow polysilicon gate structure;
- depositing a metal layer on the top surface of said fourth insulator layer, on the top surface of said heavily doped source and drain region, and on top surface of said narrow polysilicon gate structure, exposed in said contact hole;
- and
- patterning of said metal layer to form metal contact structures to said heavily doped source and drain region, and to said narrow polysilicon gate structure.