# US 5,702,966 A · Method of manufacturing a semiconductor memory device

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- Number: US 5,702,966 A
- Document ID: US5702966A
- Status: Granted
- Kind: A
- Application number: 08/732,669
- Filed: 1996-10-16
- Granted: 1997-12-30
- Earliest claimed: 1993-11-30
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Junichiro Noda; Daisuke Tohyama
- Web page: https://patentgrep.com/patent/US5702966A

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- Y10S 438/981: Utilizing varying dielectric thickness
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.

## Claims

### Claim 1

A method of manufacturing a nonvolatile semiconductor memory device containing a select MOS transistor and a data storage MOS transistor, comprising the steps of:
forming a first region by implanting impurities of a second conductivity type into an element region of a semiconductor substrate of a first conductivity type;
forming a first insulating film in said element region;
removing said first insulating film on said first region and a region adjacent to said first region;
forming a second insulating film thicker than said first insulating film on said semiconductor substrate exposed in said element region;
forming a first conducting film on said first and second insulating films;
forming a hole in a position of said first conducting film;
forming a third insulating film on first conductive film and in the hole;
forming a second conducting film on said third insulating film;
etching said second conducting film, said third insulating film, said first conducting film, said second insulating film, and said first insulating film in sequence, so as to form a gate electrode of said select MOS transistor and a control gate electrode and a floating-gate electrode of said data storage MOS transistor, said control gate electrode and said floating-gate electrode having a first portion and a second portion above said element region, said first portion being placed above said first region, and said first portion and said second portion being spaced apart on said element region and connected to each other on a field region; and
implanting impurities of a second conductivity type into said element region with the gate electrode of said select MOS transistor and the control gate electrode and floating-gate electrode of said data storage MOS transistor as a mask, so as to form a second region in said element region between said first portion and said second portion and a third region in said element region between said first portion and the gate electrode of said select MOS transistor.

### Claim 2 (depends on 1)

A method according to claim 1, wherein said second and third regions are formed so that the impurity concentration in said second and third regions are lower than that in said first region.

### Claim 3 (depends on 1)

A method according to claim 1, wherein said first, second, and third regions are formed so as to function as a source region of said select MOS transistor and a drain region of said data storage MOS transistor.

### Claim 4 (depends on 1)

A method of according to claim 1, wherein said first region is formed by implanting impurities of more than two dopants whose diffusion coefficient differs from each other in said element region.