# US 5,702,965 A · Flash memory cell and method of making the same

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- Number: US 5,702,965 A
- Document ID: US5702965A
- Status: Granted
- Kind: A
- Application number: 08/666,013
- Filed: 1996-06-19
- Granted: 1997-12-30
- Earliest claimed: 1995-06-24
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Jeoung Woo Kim
- Web page: https://patentgrep.com/patent/US5702965A

## CPC

- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A highly efficient split-gate type flash memory cell with an insulation spacer of an ONO or ON structure formed at the side walls of the floating gate according to the present invention can improve program and erasure capabilities of the cell by preventing reduction of the coupling ratio and leakage of electrons through the floating gate and the control gate.

## Claims

### Claim 1

A method of making a flash memory cell in a semiconductor device, comprising:
sequentially forming a tunnel oxide film, a first polysilicon layer and an oxide film on a silicon substrate;
patterning said oxide film and said first polysilicon layer to form a floating gate on said substrate;
forming source and drain regions in said silicon substrate;
forming an insulating film on said tunnel oxide film, said first polysilicon layer and said oxide film after forming said source and drain regions, and forming an insulating film spacer at side walls of said oxide film and floating gate through an isotropic etching process, said insulating film having an ONO structure in which an underlying oxide film, a nitride film and an upper oxide film are sequentially stacked;
removing a portion of said oxide film remaining on said floating gate and performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;
forming a second polysilicon layer on said select-gate oxide film, said insulating film spacer and said dielectric film; and patterning said second polysilicon layer to form a control gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein said underlying oxide film is a CVD oxide film.

### Claim 3 (depends on 1)

The method of claim 1, wherein said underlying oxide film is a thermal oxide film.

### Claim 4

A method of making a flash memory cell in a semiconductor device, comprising:
sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate;
patterning said first polysilicon layer to form a floating gate;
forming source and drain regions in said silicon substrate;
forming an insulating film on said tunnel oxide film and said first polysilicon layer after forming said source and drain regions, and forming an insulating film spacer at side walls of said floating gate through an isotropic etching process, said insulating film having an ONO structure in which an underlying oxide film, a nitride film and an upper oxide film are sequentially stacked;
performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;
forming a second polysilicon layer on said select-gate oxide film, said insulating film spacer and said dielectric film; and patterning the second polysilicon layer to form a control gate.

### Claim 5 (depends on 4)

The method of claim 4, wherein said underlying oxide film is a CVD oxide film.

### Claim 6 (depends on 4)

The method of claim 4, wherein said underlying oxide film is a thermal oxide film.

### Claim 7

A method of making a flash memory cell in a semiconductor device, comprising:
sequentially forming a tunnel oxide film, a first polysilicon layer and an oxide film on a silicon substrate;
patterning said oxide film and said first polysilicon layer to form a floating gate;
forming source and drain regions in said silicon substrate;
forming an insulating film on said tunnel oxide film, said first polysilicon layer and said oxide film after forming said source and drain regions, and forming an insulating film spacer at side walls of said oxide film and floating gate through an isotropic etching process, said insulating film having an ON structure in which an oxide film and a nitride film are sequentially stacked with respect to each other;
removing a portion of said oxide film remaining on said floating gate and performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;
forming a second polysilicon layer on said select-gate oxide film, said insulating film spacer and said dielectric film; and
patterning said second polysilicon layer to form a control gate.

### Claim 8 (depends on 7)

The method of claim 7, wherein said oxide film is a CVD oxide film.

### Claim 9 (depends on 7)

The method of claim 7, wherein said oxide film is a thermal oxide film.

### Claim 10

A method of making a flash memory cell in a semiconductor device, comprising:
sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate;
patterning said first polysilicon layer to form a floating gate;
forming source and drain regions in said silicon substrate;
forming an insulating film on the said tunnel oxide film and said first polysilicon layer after forming said source and drain regions, and forming an insulating film spacer at side walls of said floating gate through an isotropic etching process, said insulating film having an ON structure in which an oxide film and a nitride film are sequentially stacked with respect to each other;
removing a portion of said oxide film remaining on said floating gate and performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;
forming a second polysilicon layer on said select-gate oxide film, and said insulating film spacer and said dielectric film; and
pattering said second polysilicon layer to form a control gate.

### Claim 11 (depends on 10)

The method of claim 10, wherein said oxide film is a CVD oxide film.

### Claim 12 (depends on 10)

The method of claim 10, wherein said oxide film is a thermal oxide film.