# US 5,702,963 A · Method of forming high density electronic circuit modules

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- Number: US 5,702,963 A
- Document ID: US5702963A
- Status: Granted
- Kind: A
- Application number: 08/333,226
- Filed: 1994-11-02
- Granted: 1997-12-30
- Earliest claimed: 1990-12-31
- Assignees: Kopin Corporation
- Inventors: Duy-Pach Vu; Brenda Dingle; Ngwe Cheong
- Web page: https://patentgrep.com/patent/US5702963A

## CPC

- H10D 86/0214: {using temporary substrates}
- A61B 3/113: for determining or recording eye movement
- G02B 27/0093: {with means for monitoring data relating to the user, e.g. head-tracking, eye-tracking}
- G02B 27/017: {Head mounted}
- G02B 27/0172: {characterised by optical features}
- G02F 1/133526: {Lenses, e.g. microlenses or Fresnel lenses}
- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element}
- G02F 1/136277: {formed on a semiconductor substrate, e.g. of silicon}
- G09G 3/30: using electroluminescent panels
- G09G 3/36: using liquid crystals
- H04N 5/7441: {the modulator being an array of liquid crystal cells}
- H04N 9/3141: {Constructional details thereof (details not peculiar to the presence of an electronic spatial light modulator G03B21/14)}
- H05B 33/12: Light sources with substantially two-dimensional [2D] radiating surfaces
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- H10W 72/0198: {batch processes}
- H10W 90/00: Package configurations
- G02B 5/30: Polarising elements (light-modulating devices with active elements G02F1/00)
- G02B 2027/0132: {comprising binocular systems}
- G02B 2027/0138: {comprising image capture systems, e.g. camera}
- G02B 2027/0187: {slaved to motion of at least a part of the body of the user, e.g. head, eye}
- G02B 2027/0198: {System for aligning or maintaining alignment of an image in a predetermined direction}
- G02F 1/13336: {Combining plural substrates to produce large-area displays, e.g. tiled displays}
- G02F 1/13473: {for wavelength filtering or for colour display without the use of colour mosaic filters}
- G02F 1/13613: {the semiconductor element being formed on a first substrate and thereafter transferred to the final cell substrate}
- G02F 2202/105: single crystal Si
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3607: {for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels (display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127)}
- G09G 3/3614: {Control of polarity reversal in general}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 2300/023: Display panel composed of stacked panels
- G09G 2300/0809: Several active elements per pixel in active matrix panels
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2320/041: Temperature compensation
- G09G 2320/043: Preventing or counteracting the effects of ageing
- G09G 2340/0464: Positioning
- G09G 2370/042: for monitor identification
- H01S 5/0217: {Removal of the substrate}
- H01S 5/423: {having a vertical cavity}
- H04N 5/70: Circuit details for electroluminescent devices
- H04N 5/7491: {of head mounted projectors}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- Y10S 148/135: Removal of substrate
- Y10S 148/15: Silicon on sapphire SOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- A61B: DIAGNOSIS; SURGERY; IDENTIFICATION (usefulness limited to only animals A61D)
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates Using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.

## Claims

### Claim 1

A method of fabricating a double gate MOSFET device comprising:
providing a layer of silicon over a insulating layer;
doping the silicon layer to produce a source region and a drain region each of a first conductivity type separated by a channel region of a second conductivity type such that conductivity junctions exist between the source and channel regions and between the drain and channel regions;
forming a first gate over the channel region of the silicon layer;
attaching conductive contacts to the source, drain and first gate;
removing a region of the insulating layer to expose a backside region of the silicon layer;
forming a second gate adjacent the backside region of the silicon layer over the channel region opposite the first gate; and
attaching a conductive contact to the second gate.

### Claim 2 (depends on 1)

The method of claim 1 further comprising electrically connecting the first gate and second gate contacts.

### Claim 3 (depends on 1)

The method of claim 1 further comprising after the step of attaching the conductive contacts to the first gate, attaching the silicon layer to a second substrate with an adhesive layer.

### Claim 4 (depends on 1)

The method of claim 1 further comprising forming a plurality of MOSFETs in the layer of silicon to form a silicon-on-insulator structure.

### Claim 5 (depends on 1)

The method of claim 1 further comprising forming a plurality of circuit elements in the layer of silicon, each circuit element including a double gate MOSFET, transferring the circuit elements onto a common module body and interconnecting the circuit elements.

### Claim 6 (depends on 1)

The method of claim 1 further comprising attaching a second silicon layer to the layer of silicon having the double gate MOSFET formed therein with an adhesive layer.

### Claim 7

A method of fabricating a plurality of field effect transistors comprising:
providing a first layer of silicon on an insulating oxide layer that is positioned on an underlying silicon substrate;
doping the first layer of silicon to produce a source region and a drain region separated by a channel region;
forming a first gate over the channel region of the first layer of silicon to form a first field effect transistor;
providing a second layer of silicon on an insulating oxide layer that is positioned on a second underlying silicon substrate, the second layer of silicon having a second field effect transistor;
attaching a second substrate to the second layer of silicon and removing the second underlying silicon substrate;
attaching the second layer of silicon to the first layer of silicon with an adhesive layer;
removing the second substrate; and
interconnecting the first field effect transistor formed with the first layer of silicon to the field effect transistor formed with the second layer of silicon to form an integrated circuit.

### Claim 8 (depends on 7)

The method of claim 7 further comprising removing a region of the insulating layer to expose a region of the first layer of silicon; and
forming a second gate adjacent the exposed region of the first layer of silicon over the channel region opposite the first gate.

### Claim 9 (depends on 8)

The method of claim 8 further comprising electrically connecting the first gate and second gate.

### Claim 10 (depends on 7)

The method of claim 7 further comprising attaching the second layer of silicon to the first layer of silicon with an adhesive layer and connecting the first transistor to the second transistor through an opening in the adhesive layer.

### Claim 11 (depends on 7)

The method of claim 7 further comprising forming a plurality of circuit elements in at least one layer of silicon in a plurality of integrated circuits, each circuit element including a double gate MOSFET, transferring the integrated circuits onto a common module body and interconnecting the circuit elements.

### Claim 12 (depends on 7)

The method of claim 7 further comprising forming a plurality of circuit elements in at least one layer of silicon in a plurality of integrated circuits, each circuit element including a double gate MOSFET, transferring the integrated circuits onto a common module body and interconnecting the circuit elements.

### Claim 13 (depends on 7)

The method of claim 7 further comprising forming a CMOS device in the first layer of silicon.

### Claim 14 (depends on 7)

The method of claim 7 further comprising forming a memory device in one or more of the layers of silicon to form the integrated circuit.

### Claim 15 (depends on 7)

The method of claim 7 further comprising forming a processing circuit in one or more of the layers of silicon to form the integrated circuit.

### Claim 16

A method of fabricating an integrated circuit, comprising the steps of:
forming a first circuit layer having a first plurality of transistor circuit elements formed in a first silicon layer on an insulating oxide layer that is positioned on a silicon substrate;
forming a second circuit layer having a second plurality of transistor circuit elements;
adhering the first circuit layer to the second circuit layer with a layer of adhesive material; and
interconnecting the first circuit layer with the second circuit layer through the layer of adhesive material, the silicon substrate being removed from the first circuit layer to form a thin film first circuit layer extending over the second circuit layer.

### Claim 17 (depends on 16)

The method of claim 16 further comprising the step of vertically positionally the second circuit layer relative to the first circuit layer before the adhering step.

### Claim 18 (depends on 16)

The method of claim 16 wherein the steps of forming the first and second circuit layers comprises forming field effect transistors.

### Claim 19 (depends on 18)

The method of claim 18 wherein the step of forming field effect transistors comprises forming MOSFETs.

### Claim 20 (depends on 16)

The method of claim 16 wherein the step of forming the first circuit layer comprises forming a layer of semiconductor material to strengthen the interconnected circuit elements.

### Claim 21 (depends on 16)

The method of claim 16 wherein the step of forming the second circuit layer comprises forming a layer of semiconductor material on an insulating oxide layer extending over a semiconductor substrate, transferring the layer of semiconductor material and the insulating oxide layer to a second substrate with an epoxy adhesive.

### Claim 22 (depends on 16)

The method of claim 16 wherein the step of interconnecting comprises forming an electrically conductive material between a first select circuit element formed in the first circuit layer and a second select circuit element formed in the second circuit layer.

### Claim 23 (depends on 22)

The method of claim 22 wherein the step of forming an electrically conductive material includes forming via openings between the select circuit elements.

### Claim 24 (depends on 16)

The method of claim 16 further comprising forming a CMOS device in one or more of the layers of silicon to form the integrated circuit.

### Claim 25 (depends on 16)

The method of claim 16 further comprising forming a processing circuit in one or more of the layers of silicon to form the integrated circuit.

### Claim 26 (depends on 16)

The method of claim 16 further comprising forming a memory circuit in one or more of the layers of silicon to form the integrated circuit.

### Claim 27 (depends on 16)

The method of claim 16 further comprising transferring the first circuit layer including the insulating oxide from the silicon substrate to a second substrate.

### Claim 28 (depends on 27)

The method of claim 27 further comprising removing portions of the insulating oxide to device process a second side of the first circuit layer.

### Claim 29 (depends on 16)

The method of claim 16 further comprising forming a conductive material between the first circuit layer and the second circuit layer.

### Claim 30 (depends on 29)

The method of claim 29 wherein the step of forming the conductive material comprises forming an electrical shielding layer.

### Claim 31 (depends on 29)

The method of claim 29 wherein the step of forming the conductive material further comprises forming a conductive layer between the first silicon layer and the second circuit layer.

### Claim 32 (depends on 16)

The method of claim 16 wherein the step of adhering the first circuit layer to the second circuit layer with an epoxy adhesive.

### Claim 33 (depends on 16)

The method of claim 16 further comprising removing the silicon substrate with an etching process.

### Claim 34 (depends on 16)

The method of claim 16 wherein the adhering step comprises bonding the first circuit layer to the second circuit layer with a cycloaliphatic anhydride.