# US 5,702,960 A · Method for manufacturing polysilicon thin film transistor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,702,960 A
- Document ID: US5702960A
- Status: Granted
- Kind: A
- Application number: 08/396,162
- Filed: 1995-02-27
- Granted: 1997-12-30
- Earliest claimed: 1994-02-25
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Kyusun Moon
- Web page: https://patentgrep.com/patent/US5702960A

## CPC

- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a polysilicon thin film transistor in which a lower gate pattern is formed by stacking a conductive material on a transparent substrate, then a buffering insulating layer, a polysilicon layer, a gate insulating layer and a conductor layer are formed by sequentially stacking an insulating material, a polysilicon, an insulating material and a conductive material. Then a photoresist pattern is formed by coating a photoresist and exposing the backside of the photoresist using the lower gate pattern, and thereafter, an upper gate pattern is formed by etching the conductor layer using the photoresist pattern as a mask. The method of the present invention is suitable for manufacturing the polysilicon thin film transistor of an offset structure or of an LDD structure.

## Claims

### Claim 1

A method for manufacturing a thin film transistor comprising the steps of:
preparing a transparent substrate having a top face and a bottom face;
forming a lower gate pattern on said top face of said transparent substrate;
depositing a first insulating layer, a semiconductor layer, a second insulating layer, and a conducting layer successively over said lower gate pattern;
forming a first photoresist layer on said conducting layer;
patterning said first photoresist layer by exposing through said bottom face of said transparent substrate using said lower gate pattern as a mask;
forming an upper gate pattern by etching said conducting layer using said patterned first photoresist layer as a mask, said upper gate pattern being formed so as to have a width smaller than a width of said lower gate pattern;
removing said patterned first photoresist layer;
forming a second photoresist layer on said upper gate pattern;
patterning said second photoresist layer by exposing through said bottom face of said transparent substrate using said lower gate pattern as a mask, said second photoresist layer being patterned so that said patterned second photoresist layer has a width larger than said width of said upper gate pattern;
implanting ions into said semiconductor layer utilizing said patterned second photoresist layer as a mask; and
removing said patterned second photoresist layer.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising a step of implanting ions into said implanted semiconductor layer utilizing said upper gate pattern as a mask after removing said patterned second photoresist layer.

### Claim 3

A method for manufacturing a thin film transistor comprising the steps of:
preparing a transparent substrate having a top face and a bottom face;
forming a lower gate pattern on said top face of said transparent substrate;
forming a first insulating layer, a semiconductor layer, a second insulating layer and a negative photoresist layer successively over said lower gate pattern;
patterning said negative photoresist layer by exposing through said bottom face of said transparent substrate using said lower gate pattern as a mask;
forming a conductor layer on said patterned negative photoresist layer and exposed portions of said second insulating layer;
forming an upper gate pattern by removing said patterned negative photoresist layer and by removing portions of said conductor layer formed on said patterned negative photoresist layer, said upper gate pattern being formed so as to have a width smaller than a width of said lower gate pattern;
forming a second photoresist layer on said upper gate pattern;
patterning said second photoresist layer by exposing through said bottom face of said transparent substrate using said lower gate pattern as a mask, said second photoresist layer being patterned so that said patterned second photoresist layer has a width larger than said width of said upper gate pattern;
implanting ions into said semiconductor layer utilizing said patterned second photoresist layer as a mask; and
removing said patterned second photoresist layer.

### Claim 4 (depends on 3)

The method according to claim 3, further comprising a step of implanting ions into said implanted semiconductor layer utilizing said upper gate pattern as a mask after removing said patterned second photoresist layer.