Method for making an isolated vertical transistor

A process for making a vertical PNP transistor, comprising the steps of:

• forming a highly doped N type buried isolation region in a P type semiconductor substrate to vertically isolate a top portion of said substrate from a bottom portion of said substrate;
• forming a highly doped N type isolation region to encompass and laterally isolate said vertically isolated top portion of said substrate;
• diffusing a N type base impurity into said encompassed top portion of said substrate to form a base region;
• diffusing a P type emitter impurity into said base region to form an emitter region diffusing a P type emitter impurity into said base region to form an emitter region;
• and performing at least a portion of a BiCMOS process simultaneously with said steps of forming the buried isolation region, diffusing the base impurity, and diffusing the emitter impurity, wherein said BiCMOS process includes the step of forming an EEPROM having a tunnel diode for charge transfer to a floating gate, and wherein said step of diffusing the base impurity is performed simultaneously with a tunnel diode diffusion.

A process for making a vertical transistor on a highly doped semiconductor substrate of first conductivity type, comprising:

• epitaxially growing a first lightly doped layer of semiconductor material of said first conductivity type on a surface of said semiconductor substrate;
• introducing a buried layer impurity of second conductivity type into a surface region of said first lightly doped layer of semiconductor material that will underlie the vertical transistor;
• epitaxially growing a second layer of lightly doped semiconductor material of said first conductivity type on said first lightly doped layer of semiconductor material and said buried layer impurity;
• diffusing an isolation impurity into said second layer of semiconductor material to laterally enclose an island of said second layer of semiconductor material above said buried layer impurity;
• diffusing a base impurity of said second conductivity type into a base region of said enclosed region of said second layer of lightly doped semiconductor material;
• diffusing an emitter impurity of said first conductivity type into an emitter region within said base region;
• and diffusing a collector resistivity adjusting impurity into said second layer of semiconductor material prior to said step of diffusing the base impurity.

A process for making a vertical transistor on a highly doped semiconductor substrate of first conductivity type, comprising:

• epitaxially growing a first lightly doped layer of semiconductor material of said first conductivity type on a surface of said semiconductor substrate;
• introducing a buried layer impurity of second conductivity type into a surface region of said first lightly doped layer of semiconductor material that will underlie the vertical transistor;
• epitaxially growing a second layer of lightly doped semiconductor material of said first conductivity type on said first lightly doped layer of semiconductor material and said buried layer impurity;
• diffusing an isolation impurity into said second layer of semiconductor material to laterally enclose an island of said second layer of semiconductor material above said buried layer impurity;
• diffusing a base impurity of said second conductivity type into a base region of said enclosed region of said second layer of lightly doped semiconductor material;
• diffusing an emitter impurity of said first conductivity type into an emitter region within said base region;
• performing a BiCMOS process simultaneously with said steps of diffusing the isolation impurity, diffusing the base impurity, and diffusing the emitter impurity, wherein said BiCMOS process includes the step of forming an EEPROM having a tunnel diode for charge transfer to a floating gate, and wherein said step of diffusing the base impurity is performed simultaneously with a tunnel diode diffusion.