High-performance non-volatile RAM protected write cache accelerator system employing DMA and data transferring scheme

A data storage system that is coupleable between a plurality of non-volatile data storage devices and a host computer system to manage the exchange of data between said plurality of non-volatile data storage devices and said host computer system, said data storage system comprising:

• a) a plurality of data transfer channels coupleable respectively to said data storage devices, each said data transfer channel including:
• i) a channel buffer;
• and
• ii) a channel controller that, with respect to said host computer system, autonomously controls the transfer of data between a respective pair of said channel buffers and said non-volatile data storage devices;
• b) a non-volatile random access memory for storing control information and cache page data, said control information corresponding to said cache page data;
• c) an interface for coupling said data storage system with said host computer system;
• d) a data bus permitting selective transfer of said cache page data between said data transfer channels, said non-volatile random access memory, and said interface;
• and
• e) a controller, coupled to said data bus, that directs the selective transfer of said cache page data through said interface, said non-volatile random access memory, and said data transfer channels, said controller including a direct memory access controller that manages burst transfers of predetermined cache page data between said non-volatile random access memory and said channel buffers, said controller maintaining said predetermined cache page data and corresponding said control information until the transfer of said predetermined cache page data to said non-volatile data storage devices until the transfer is complete.