US 5,701,434 AGranted

Interleave memory controller with a common access queue

AssigneeHitachi, Ltd.

InventorTakayuki Nakagawa

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Abstract

A computer system is composed of a processor 10, a memory control circuit 70, and interleaved bank memories 41 through 44. The memory control circuit contains random access queue entries 71 through 73 commonly used by all memories 41 through 44. A bypass 80 allows direct bank access without writing memory access requests to the queue entries 71 through 73. Sequence is maintained by the in-bank access sequence assurance circuits 90. Because the queue entries 71 through 73 allow memory control without providing the number of entries in an integral multiple of the number of banks, the entire circuit scale is reduced. All bank busy circuits in the system are integrated on a single LSI to reduce delay, thereby enhancing processing speed. The bypass 80 eliminates queue read/write cycles from data access time, thereby enhancing processing speed.

Claims28

Dependent claims

A memory control circuit comprising:

means for receiving access requests entered from outside said memory control circuit and issued to an interleaved memory having a plurality of banks;
a single access queue connected to said means and storing the access requests commonly for said plurality of banks;
and
means controlling said access queue for storing the access requests while waiting for said plurality of banks to be taken out of a wait state;
an access sequencing circuit reading the access requests from said access queue and assuring access sequence of the access requests;
a circuit for detecting that a first bank identified by a first access request in said means for receiving is idle;
a circuit for detecting that said access queue contains no access request addressed to said first bank;
and
a bypass responsive to when said first bank is idle and when said access queue contains no access request addressed to said first bank, to transfer the first access request from said means for receiving to said first bank without passing the first access request through said access queue.

6 more elements

A computer system, comprising:

an interleaved memory;
a device for issuing memory access requests, each with a requested bank address, to the interleaved memory;
said interleaved memory having a plurality of banks of memory to which the memory access requests are addressed;
a priority control circuit having a latch receiving and latching in the memory access requests at a controlled timing in an order of their receipt;
a queue control circuit reading the requested bank address of the memory access requests and generating control signals;
a separate bank busy counter dedicated to each of said banks and coupled to said queue control circuit;
a single random access queue having a plurality of random access entries, each of said entries being commonly coupled between said latch and each of said memory banks;
said priority control circuit, said queue control circuit, said latch, said bank busy counters, and said random access queue being integrated on a single LSI chip as a memory control circuit;
said memory control circuit controlling transfer of each of the memory access requests to a bank corresponding to the requested bank address and in response thereto starting a fixed time interval busy count in the bank busy counter dedicated to the bank corresponding to the requested bank address, placing further memory access requests to the bank corresponding to the requested bank address in a wait state during the busy count, and releasing a next one of the memory access requests to the bank corresponding to the requested address bank from the wait state at expiration of the busy count.

6 more elements

Dependencies are inferred from the claim text.