Semiconductor device having first and second stacked semiconductor layers, with electrical contact to the first semiconductor layer
AssigneeHitachi, Ltd.
InventorsHidetoshi Matsumoto, Masamitsu Yazawa, Kenji Hiruma
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Abstract
A semiconductor device (e.g., hetero-junction field-effect transistor) which has decreased capacitance between the gate and drain, and which has decreased source resistance, is provided. Structure in which a contact layer 6 comes in contact with the side surfaces of a channel layer 3 but does not come in contact with the side surfaces of a barrier layer 4 enables capacitance between the gate and drain to be decreased. This capacitance can be decreased down to 1.5 pF per 10 .mu.m of the width.
Claims48
A contact, for a semiconductor device, comprising a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer so as to form a junction therebetween, the second semiconductor layer having a lower surface adjacent the first semiconductor later and side surfaces extending from the lower surface in a direction away from the first semiconductor layer, and impurity-doped third semiconductor layers positioned such that the first semiconductor layer is between the third semiconductor layers, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, the third semiconductor layers being in electrical contact with the first semiconductor layer and physically contacting opposed sides of the first semiconductor layer, said third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.
A semiconductor device comprising at least one field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and being of a different semiconductor material than that of the first semiconductor layer so as to form a hetero-junction between the first and second semiconductor layers, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, a gate electrode overlying the second semiconductor layer, a channel being formed in the first semiconductor layer under the gate electrode, third semiconductor layers at opposed sides of the first semiconductor layer, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, the third semiconductor layers being impurity-doped, and source and drain electrodes respectively in contact with the third semiconductor layers, wherein the third semiconductor layers are in physical contact with the opposed sides of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.
A semiconductor device comprising a field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having an electron affinity which is smaller than that of the first semiconductor layer, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, and a gate electrode formed on the second semiconductor layer, wherein the first semiconductor layer is arranged between third semiconductor layers to which n-type impurities have been added, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, and the third semiconductor layers are connected to source and drain electrodes, the third semiconductor layers being in physical contact with side surfaces of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.
A semiconductor device comprising a field-effect transistor having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a lower surface adjacent the first semiconductor layer and side surfaces extending from the lower surface, in a direction away from the first semiconductor layer, each of the first and second semiconductor layers having a sum of an electron affinity and a band gap, the sum being larger for the second semiconductor layer than for the first semiconductor layer, and a gate electrode formed on the second semiconductor layer, wherein the first semiconductor layer is arranged between third semiconductor layers to which p-type impurities have been added, the third semiconductor layers being selectively grown and being formed of different layers than that of said first semiconductor layer, and the third semiconductor layers are connected to source and drain electrodes, the third semiconductor layers being in physical contact with side surfaces of the first semiconductor layer, the third semiconductor layers physically contacting the second semiconductor layer without physically contacting the side surfaces of the second semiconductor layer.
Dependencies are inferred from the claim text.