# US 5,700,549 A · Structure to reduce stress in multilayer ceramic substrates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,700,549 A - Document ID: US5700549A - Status: Granted - Kind: A - Application number: 08/668,668 - Filed: 1996-06-24 - Granted: 1997-12-23 - Earliest claimed: 1996-06-24 - Assignees: International Business Machines Corporation - Inventors: John J. Garant; Richard F. Indyk - Web page: https://patentgrep.com/patent/US5700549A ## CPC - H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion} - B32B 18/00: Layered products essentially comprising ceramics, e.g. refractory products - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - C04B 2237/32: Ceramic - C04B 2237/62: Forming laminates or joined articles comprising holes, channels or other types of openings - C04B 2237/64: Forming laminates or joined articles comprising grooves or cuts - C04B 2237/68: Forming laminates or joining articles wherein at least one substrate contains at least two different parts of macro-size, e.g. one ceramic substrate layer containing an embedded conductor or electrode - H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 3/4053: {by thick-film techniques} - H05K 3/4611: {by laminating two or more circuit boards (H05K3/4652 takes precedence)} - H05K 3/4629: {laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets} - H05K 2201/068: wherein the coefficient of thermal expansion is important - H05K 2201/09781: Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components - Y10T 29/49163: with sintering of base - Y10T 156/1056: Perforating lamina - Y10T 428/24917: including metal layer - Y10T 428/24926: including ceramic, glass, porcelain or quartz layer - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - B32B: LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - C04B: LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE {(roofing granules E04D7/005)}; CERAMICS (devitrified glass-ceramics C03C10/00); REFRACTORIES; TREATMENT OF NATURAL STONE - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A multilayer ceramic substrate for microelectronics includes stress relief pads to reduce stress in the vicinity of functional vias penetrating through multiple ceramic layers. The stress relief pads are located only on the major surface of a ceramic layer and accordingly do not prevent wiring from being placed directly below the stress relief pads on the bottom surface of the same layer or the top surface of the imediately underlying layer. The invention also includes the method of making the multilayer ceramic substrate with stress relief pads. ## Claims ### Claim 1 A multilayer ceramic substrate for microelectronics comprising: a plurality of ceramic layers arranged in sequential layers, each layer having a major surface; a plurality of electrically conductive wires formed on the major surfaces of the ceramic layers; a plurality of electrically conductive functional vias, each functional via extending through one or more of the ceramic layers and electrically connecting to one or more of the wires; and a plurality of stress relief pads formed on the major surface of at least one of the ceramic layers in the vicinity of selected ones of the functional vias, the stress relief pads reducing stress formed in the at least one of the ceramic layers during ceramic sintering manufacturing steps as a result of thermal coefficient of expansion differences between the selected ones of the functional vias and the ceramic substrate. ### Claim 2 (depends on 1) A multilayer ceramic substrate for microelectronics according to claim 1 wherein the stress relief pads comprise circular pads. ### Claim 3 (depends on 1) A multilayer ceramic substrate for microelectronics according to claim 1 wherein the stress relief pads are formed of molybdenum. ### Claim 4 (depends on 1) A multilayer ceramic substrate for microelectronics according to claim 1 wherein at least one stress relief pad is located directly above a wire located directly below said at least one stress relief pad. ### Claim 5 (depends on 1) A multilayer ceramic substrate for microelectronics according to claim 1 wherein the plurality of stress relief pads are located at midpoints between pairs of the functional vias. ### Claim 6 (depends on 1) A multilayer ceramic substrate for microelectronics according to claim 1 further comprising a plurality of stress relief vias located in the vicinity of the selected ones of the functional vias, the stress relief vias further reducing stress in the ceramic layers in the vicinity of the selected ones of the functional vias. ### Claim 7 (depends on 6) A multilayer ceramic substrate for microelectronics according to claim 6 wherein the stress relief vias extend through a single one of the ceramic layers. ### Claim 8 (depends on 6) A multilayer ceramic substrate for microelectronics according to claim 6 wherein the stress relief vias are located on an opposite side of the functional vias from corresponding ones of the stress relief pads. ### Claim 9 (depends on 1) A multilayer ceramic substrate for microelectronics according to claim 1 wherein multiple ones of the stress relief pads are located in the vicinity of each of the selected ones of the functional vias to further reduce stress in the ceramic layers between the functional vias. ### Claim 10 (depends on 9) A multilayer ceramic substrate for microelectronics according to claim 9 further comprising a plurality of stress relief vias located in the vicinity of the selected ones of the functional vias, and wherein multiple ones of the stress relief vias are located in the vicinity of the selected ones of the functional vias.