# US 5,700,349 A · Method for forming multi-layer interconnections > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,700,349 A - Document ID: US5700349A - Status: Granted - Kind: A - Application number: 08/585,772 - Filed: 1996-01-16 - Granted: 1997-12-23 - Earliest claimed: 1995-01-20 - Assignees: Sony Corporation - Inventors: Masanori Tsukamoto; Tetsuo Gocho - Web page: https://patentgrep.com/patent/US5700349A ## CPC - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of forming a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-hole is used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etch stop layer covering the entire surface of the substrate, said etching stop layer being slower in etch rate than said interlayer insulating film; anisotropically etching said interlayer insulating film in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole; and filling said through-hole with an electrically conductive material. ## Claims ### Claim 1 A method of forming a semiconductor device having a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-holes are used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of: forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on a lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etching stop layer covering the entire surface of the semiconductor device, said etching stop layer being slower in etch rate than said interlayer insulating layer; forming the insulating film so as to be substantially planer and so as to cover the entire surface of said semiconductor device for completing a through hole; and anisotropically etching said interlayer insulating layer in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole; and filling said through-hole with an electrically conductive material. ### Claim 2 (depends on 1) The method as claim in claim 1, wherein said interlayer insulating layer is formed of an SiO.sub.x based material and wherein said etching stop layer is formed using at least one insulating material selected from the group consisting of an Si.sub.x N.sub.y based material, an Si.sub.x O.sub.y N.sub.z based material and an Al.sub.x O.sub.y based material, wherein x, y and z are whole numbers. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein the opening size of said through-hole is 1 to 1.2 times the applicable minimum processing size. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein the mid interconnection layer and the lower interconnection layer are a gate electrode and a source/drain region of a MOS transistor, respectively. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein said electrically conductive material is the same material of the upper interconnection layer. ### Claim 6 (depends on 1) The method as claimed in claim 1, wherein said electrically conductive material comprises an Al-based material. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein said electrically conductive material is different than that of the upper interconnection layer. ### Claim 8 (depends on 7) The method as claimed in claim 7, wherein said electrically conductive material comprises a W-plug. ### Claim 9 (depends on 1) The method as claimed in claim 1, further comprising a step of forming a film in the through-hole to obtain an excellent coverage. ### Claim 10 A method for forming a semiconductor device having a multi-layer interconnection by forming a through-hole by boring through an interlayer insulating film in a spacing between interconnection layers of two neighboring mid interconnection layers for establishing electrical conduction between an upper interconnection layer and a lower interconnection layer via said through-hole, comprising the steps of: forming an offset insulating film on said mid interconnection layer with the same pattern as the mid interconnection layer; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film, said sidewall insulating film being slower in etch rate than said interlayer insulating film; forming the interlayer insulating film so as to be substantially planar and so as to cover the entire surface of said semiconductor device for completing a through-hole; and anisotropically etching said interlayer insulating layer in an opening size smaller than the spacing between the interconnecting; filling said through-hole with an electrically conductive material. ### Claim 11 (depends on 10) The method as claimed in claim 10, wherein said interlayer insulating film is formed of an SiO.sub.x based material and wherein said sidewall insulating film is formed of at least one insulating material selected from among an Si.sub.x N.sub.y based material, an Si.sub.x O.sub.y N.sub.z based material and an Al.sub.x O.sub.y based material, wherein x, y and z are whole numbers. ### Claim 12 (depends on 10) The method as claimed in claim 10, wherein the opening size of said through-hole is 1 to 1.2 times the applicable minimum processing size. ### Claim 13 (depends on 10) The method as claimed in claim 10, wherein the mid interconnection layer and the lower interconnection layer are a gate electrode and a source/drain region of a MOS transistor, respectively. ### Claim 14 (depends on 10) The method as claimed in claim 10, wherein said electrically conductive material is the same as that of the upper interconnection layer. ### Claim 15 (depends on 10) The method as claimed in claim 10, wherein said electrically conductive material is different than that of the upper interconnection material. ### Claim 16 (depends on 10) The method as claimed in claim 10, further comprising a step of forming a film in the through-hole to obtain an excellent coverage.