Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions

In a computer system, which includes a processor having a plurality of dispatch queues, a method of executing instructions in a program flow comprising the steps of:

• issuing a producer instruction to one of the plurality of dispatch queues;
• storing a destination identifier of the producer instruction in a buffer;
• storing a dispatch queue identifier in the buffer, the dispatch queue identifier indicating which of the plurality of dispatch queues the producer instruction is being issued to;
• and
• identifying a consumer instruction having an operand matching the destination identifier of the producer instruction;
• and
• issuing the consumer instruction to a same dispatch queue as the producer instruction, the consumer instruction relying on execution of the producer instruction for the operand.

A computer system comprising:

• a memory subsystem storing instructions;
• a processor coupled to the memory subsystem comprising:
• a fetch unit for fetching instructions in a program flow from the memory subsystem, wherein the instructions in the program flow each have an operand and a destination identifier, the program flow including a consumer instruction and a producer instruction, the consumer instruction relying on execution of the producer instruction for an operand;
• a plurality of dispatch queues coupled to the fetch
• a plurality of execution clusters for executing instructions received from the dispatch queues, at least one of the execution clusters being coupled to each of the dispatch queues;
• and
• logic means receiving the instructions in the program flow from the fetch unit, and issuing the consumer instruction to a same dispatch queue as the producer instruction, and wherein the logic means includes a buffer storing a destination identifier of the producer instruction issued by the logic means to one of the plurality of dispatch queues, and storing queue information indicating which of the plurality of dispatch queues the producer instruction is issued to.