Back to results
US 5,699,460 AGranted
Image compression coprocessor with data flow control and multiple processing units
AssigneesArray Microsystems, Inc., Samsung Electronics Co., Ltd.
InventorsThomas G. Kopet, Bradford G. Taylor, Gerry C. Lui Kuo, Stephen D. Lew
Life of this patent
Estimating the term…
Abstract
The present invention provides an image compression/decompression coprocessor which is integrated on a single chip. The control bus has a control unit which is connected by an internal, global bus to a number of different, special purpose processing units. Each of the processing units is specifically designed to handle only certain steps in compression and decompression processes.
Claims37
An image compression coprocessor integrated on a single semiconductor chip comprising:
- control unit means for operating said coprocessor in accordance with a stored program;
- an internal bus coupled to said control unit means;
- and
- a plurality of special purpose processing means, each coupled to said bus, for performing a subset of a group of steps in an image compression/decompression process;
- wherein said control unit means contains an instruction memory for holding at least first and second programs loaded from an external host, and means for causing the execution of instructions from said first program prior to completion of said second program.
2 more elements
An image compression coprocessor integrated on a single semiconductor chip comprising:
- control unit means for operating said coprocessor in accordance with a stored program;
- an internal bus coupled to said control unit means;
- and
- a plurality of special purpose processing means, each coupled to said bus, for performing a subset of a group of steps in an image compression/decompression process;
- wherein each of said special purpose processing means have different, special purpose hardware;
- wherein said stored program is a data flow program, and said control unit means transfers instructions and data tokens to said plurality of special purpose processing means over said bus;
- a host interface port for coupling to a master host processor;
- and
- run length processor means, connected between said bus and said host interface port, for converting data between said token format and a run length format for communicating with said master host processor.
6 more elements
An image compression coprocessor integrated on a single semiconductor chip comprising:
- control unit means for operating said coprocessor in accordance with a stored program;
- an internal bus coupled to said control unit means;
- and
- a plurality of special purpose processing means, each coupled to said bus, for performing a subset of a group of steps in an image compression/decompression process;
- wherein each of said special purpose processing means have different, special purpose hardware;
- wherein said stored program is a data flow program, and said control unit means transfers instructions and data tokens to said plurality of special purpose processing means over said bus;
- a host interface port for coupling to a master host processor;
- and
- token interface means, coupled between said bus and said host interface port, for allowing said host processor to insert tokens directly and to view tokens on said bus.
6 more elements
An image compression coprocessor integrated on a single semiconductor chip comprising:
- control unit means for operating said coprocessor in accordance with a stored program;
- an internal bus coupled to said control unit means;
- and
- a plurality of special purpose processing means, each coupled to said bus, for performing a subset of a group of steps in an image compression/decompression process;
- wherein each of said special purpose processing means have different, special purpose hardware;
- wherein said stored program is a data flow program, and said control unit means transfers instructions and data tokens to said plurality of special purpose processing means over said bus;
- a semaphore register coupled to said control unit means;
- a plurality of semaphore instructions in said data flow program for modifying a count in said semaphore register upon the accessing of a token, comparing a value in said semaphore register with a value in a token and preventing a new data token from being accessed if said semaphore value exceeds a maximum value, and modifying said count upon a data token leaving said control unit.
5 more elements
An image compression coprocessor integrated on a single semiconductor chip comprising:
- control unit means for operating said coprocessor in accordance with a stored program;
- an internal bus coupled to said control unit means;
- and
- a plurality of special purpose processing means, each coupled to said bus, for performing a subset of a group of steps in an image compression/decompression process;
- wherein each of said special purpose processing means have different, special purpose hardware;
- wherein said stored program is a data flow program, and said control unit means transfers instructions and data tokens to said plurality of special purpose processing means over said bus;
- a semaphore register coupled to said control unit means;
- a plurality of instructions in said data flow program having a control field with a number;
- and
- means for comparing said number in said control field in an instruction with a count in said semaphore register and passing said instruction through said control unit means for processing when said number matches said count.
7 more elements
An image compression coprocessor integrated on a single semiconductor chip comprising:
- control unit means for operating said coprocessor in accordance with a stored program;
- an internal bus coupled to said control unit means;
- and
- a plurality of special purpose processing means, each coupled to said bus, for performing a subset of a group of steps in an image compression/decompression process;
- wherein each of said special purpose processing means have different, special purpose hardware;
- wherein said stored program is a data flow program, and said control unit means transfers instructions and data tokens to said plurality of special purpose processing means over said bus;
- a first register, wherein said program includes a CRTOKEN instruction which can be executed only once in said program, said CRTOKEN instruction being allowed to execute only if said first register has a first value, said CRTOKEN instruction causing said first register to assume a value other than said first value after execution, said coprocessor including reset means for changing said first register to said first value.
4 more elements
A processor integrated on a single semiconductor chip comprising:
- a control unit;
- a memory, coupled to said control unit, having a stored program;
- an internal bus coupled to said control unit;
- and
- a plurality of processing circuits, each coupled to said bus, for performing a subset of a group of steps in a process performed by said processor;
- wherein said stored program is a data flow program, and said control unit transfers instructions and data tokens to said plurality of processing circuits over said bus;
- wherein said data tokens are data vectors;
- a host interface port for coupling to a master host processor;
- run length processor means, connected between said bus and said host interface port, for converting data between said token format and a run length format for communicating with said master host processor.
6 more elements
A processor integrated on a single semiconductor chip comprising:
- a control unit;
- a memory, coupled to said control unit, having a stored program;
- an internal bus coupled to said control unit;
- and
- a plurality of processing circuits, each coupled to said bus, for performing a subset of a group of steps in a process performed by said processor;
- wherein said stored program is a data flow program, and said control unit transfers instructions and data tokens to said plurality of processing circuits over said bus;
- wherein said data tokens are data vectors;
- a host interface port for coupling to a master host processor;
- and
- token interface means, coupled between said bus and said host interface port, for allowing said host processor to insert tokens directly and to view tokens on said bus.
7 more elements
A processor integrated on a single semiconductor chip comprising:
- a control unit;
- a memory, coupled to said control unit, having a stored program;
- an internal bus coupled to said control unit;
- and
- a plurality of processing circuits, each coupled to said bus, for performing a subset of a group of steps in a process performed by said processor;
- wherein said stored program is a data flow program, and said control unit transfers instructions and data tokens to said plurality of processing circuits over said bus;
- wherein said data tokens are data vectors;
- a semaphore register coupled to said control unit;
- a plurality of semaphore instructions in said data flow program for modifying a count in said semaphore register upon the accessing of a token, comparing a value in said semaphore register with a value in a token and preventing a new data token from being accessed if said semaphore value exceeds a maximum value, and modifying said count upon a data token leaving said control unit.
6 more elements
A processor integrated on a single semiconductor chip comprising:
- a control unit;
- a memory, coupled to said control unit, having a stored program;
- an internal bus coupled to said control unit;
- and
- a plurality of processing circuits, each coupled to said bus, for performing a subset of a group of steps in a process performed by said processor;
- wherein said stored program is a data flow program, and said control unit transfers instructions and data tokens to said plurality of processing circuits over said bus;
- wherein said data tokens are data vectors;
- a semaphore register coupled to said control unit means;
- a plurality of instructions in said data flow program having a control field with a number;
- and
- means for comparing said number in said control field in an instruction with a count in said semaphore register and passing said instruction through said control unit means for processing when said number matches said count.
8 more elements
A processor integrated on a single semiconductor chip comprising:
- a control unit;
- a memory coupled to said control unit, having a stored program;
- an internal bus coupled to said control unit;
- and
- a plurality of processing circuits, each coupled to said bus, for performing a subset of a group of steps in a process performed by said processor;
- wherein said stored program is a data flow program, and said control unit transfers instructions and data tokens to said plurality of processing circuits over said bus;
- wherein said data tokens are data vectors;
- an internal bus interface coupled to said internal bus;
- an enabled instruction queue means, coupled to said internal bus interface, for holding instructions to be transferred to said processing circuits;
- a data token memory coupled to said internal bus interface;
- and
- an update unit, coupled to said enabled instruction queue, for providing instructions to said enabled instruction queue;
- a semaphore register;
- and
- means, coupled to said semaphore register, for modifying a count in said semaphore register upon accessing a data token in said data token memory, testing a semaphore value in said semaphore register and preventing a new data token from being accessed if said semaphore value exceeds a maximum value, and modifying said count upon a data token leaving said control unit.
12 more elements
A processor integrated on a single semiconductor chip comprising:
- a control unit;
- a memory, coupled to said control unit, having a stored program;
- an internal bus coupled to said control unit;
- and
- a plurality of processing circuits, each coupled to said bus, for performing a subset of a group of steps an a process performed by said processor;
- wherein said stored program is a data flow program, and said control unit transfers instructions and data tokens to said plurality of processing circuits over said bus;
- wherein said data tokens are data vectors;
- a first register, wherein said program includes a CRTOKEN instruction which can be executed only once in said program, said CRTOKEN instruction being allowed to execute only if said first register has a first value, said CRTOKEN instruction causing said first register to assume a value other than said first value after execution, said processor including reset means for changing said first register to said first value.
5 more elements
A processor integrated on a single semiconductor chip comprising:
- a control unit;
- a memory, coupled to said control unit, having a stored program;
- an internal global bus coupled to said control unit;
- a plurality of processing circuits, each coupled to said global bus, for performing a subset of a group of steps in a process performed by said processor;
- and
- a data token memory coupled to said global bus and accessible by each of said processing circuits;
- wherein said stored program is a data flow program, and said control unit asynchronously transfers instructions and data tokens to said plurality of processing circuits over said global bus;
- wherein said data tokens are data vectors.
5 more elements
Dependencies are inferred from the claim text.