Protocol for interrupt bus arbitration in a multi-processor system

A multi-processor (MP) system operating in accordance with a protocol for handling interrupts, the MP system comprising:

• an interrupt bus;
• a system bus;
• a plurality of processors that communicate across the system bus;
• a plurality of interrupt controller units (ICUs), each of the ICUs being coupled to the interrupt bus and a corresponding processor, each ICU including a first register that stores a task priority value of the corresponding processor, a second register that stores an identification (ID) of the ICU, and logic which receives interrupt messages on the interrupt bus and dispenses interrupts to the corresponding processor in accordance with the protocol, the protocol including first and second modes of operation,
• in the first mode of operation an interrupt request is accepted by the ICU when a destination field of the interrupt request matches the ID of the ICU;
• and
• in the second mode of operation the interrupt request is accepted by the ICU when a current priority value, which includes the task priority value, is a lowest current priority value from among the plurality of processors as determined by a bus arbitration sequence having a number of arbitration cycles.