Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor

Abstract

A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. Each processor has a register with a plurality of read only bits which uniquely identify that processor within the multi-processing system. The processor may employ this unique processor identifier to compute the base address corresponding to that processor. This enables programs which may execute independently of the processor within the multi-processing system.

Dependencies are inferred from the claim text.