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AssigneeSynopsys, Inc.
InventorsJames Beausang, Kenneth Wagner, Robert Walker
Estimating the term…
A computer implemented process and system for effectively determining a set of sequential cells with a integrated circuit design that can be scan replaced (e.g. for design for test applications) to offer significant testability while still maintaining specified optimization (e.g., area and/or timing) constraints that are applicable to the design. The novel system selects sequential cells for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design. The novel system is composed of a subtractive method and an additive method. The subtractive method inputs a fully scan replaced netlist (e.g., the sequential cells are scan replaced) that does not meet determined optimization constraints. The novel subtractive system unscans selected cells until the area and/or timing constraints are met. A flag indicates whether nor not timing is considered. Selection for unscanning is based on a testability cell list (TCL) that ranks cells by their degree of testability contribution; those cells with low degrees of testability are unscanned first. The additive process receives an unscanned netlist (original design) and scan replaces cells, using the TCL ranked list until optimization (e.g., area and/or timing) constraints of the design are violated. A flag indicates whether nor not timing is considered. The additive system iterates through the TCL list with the cells offering the most contribution for testability scan replaced first.
In a computer implemented synthesis system, a subtractive method of generating a netlist having scan replaced sequential cells and satisfying determined optimization constraints, said method comprising the computer implemented steps of:
In a computer system having a processor coupled to a bus and a memory coupled to said bus, a computer implemented subtractive method of generating a netlist having scan replaced sequential cells and satisfying determined timing and area constraints, said method comprising the computer implemented steps of:
A computer system having a processor coupled to a bus and a computer readable memory coupled to said bus, said computer readable memory including a logic program stored therein for causing said computer system to generate a netlist having scan replaced sequential cells and satisfying determined timing and area constraints, said logic program comprising:
In a computer system, an additive method of generating a netlist having scan replaced sequential cells and satisfying determined timing constraints, said method comprising the computer implemented steps of:
In a computer system, an additive method of generating a netlist having scan replaced sequential cells and satisfying determined timing and area constraints, said method comprising the computer implemented steps of:
A computer system comprising:
Dependencies are inferred from the claim text.