Nonvolatile integrated circuit memory devices having adjustable erase/program threshold voltage verification capability

Abstract

Integrated circuit memory devices include an array of NAND strings containing a plurality of EEPROM memory cells, sense amplifiers for determining whether the memory cells have been properly erased and programmed during respective erase and program verification modes of operation, an erase voltage adjusting circuit for setting a limit on a range of acceptable erase threshold voltages and a program voltage adjusting circuit for setting a limit on a range of acceptable program threshold voltages. The sense amplifier determines during an erase verification operation whether a memory cell in a NAND string has been erased to have a threshold voltage within a range of acceptable erase threshold voltages. The range of acceptable erase threshold voltages typically has an upper limit less than a predetermined reference potential (e.g., GND). For example, the sense amplifiers can be utilized to determine whether the memory cells in the string have been sufficiently erased so that their erase threshold voltages (EV.sub.th) are less than or equal to a preselected erase threshold voltage (e.g., -1 Volt). An erase voltage adjusting circuit is also provided for setting a limit on a range of acceptable erase threshold voltages by modifying an effective series resistance of the string of memory cells as seen by the sense amplifier during the erase verification operation. Here, the erase voltage adjusting circuit sets a limit by making the erase threshold voltage of a selected cell in the string appear to be too high when evaluated by the sense amplifier. This prompts a repeat erase operation to lower the threshold voltage of the selected cell.

Dependencies are inferred from the claim text.