US 5,696,639 A · Sampled amplitude read channel employing interpolated timing recovery

Abstract

A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector for detecting the digital data from the interpolated sample values.

Claims14

Dependent claims

A sampled amplitude read channel for reading information stored on a magnetic medium by detecting data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium, the pulses modulated at a predetermined baud rate, the sampled amplitude read channel comprising:

(a) a sampling clock;
(b) a sampling device, responsive to the sampling clock, for sampling the analog read signal to generate the channel sample values;
(c) interpolated timing recovery circuit, responsive to the channel sample values, for generating the interpolated sample values;
and
(d) a discrete time detector for detecting the data from the interpolated sample values;
wherein the sampling clock cycles at a rate slightly higher than the baud rate.

3 more elements

(a) a sampling clock;
(b) a sampling device, responsive to the sampling clock, for sampling the analog read signal to generate the channel sample values;
(c) interpolated timing recovery circuit, responsive to the channel sample values, for generating the interpolated sample values, comprising:
(i) an interpolator responsive to an interpolation interval .tau. proportional to a time difference between a channel sample value and a desired interpolated sample value;
(ii) a frequency offset generator for generating a frequency offset .DELTA..function. proportional to a frequency difference between the sampling clock and the baud rate;
and
(iii) a mod-Ts accumulator for accumulating, modulo-Ts, the frequency offset .DELTA..function. to generate the interpolation interval .tau. where Ts is a predetermined sample period;
and
(d) a discrete time detector for detecting the data from the interpolated sample values.

6 more elements

Dependencies are inferred from the claim text.

Sampled amplitude read channel employing interpolated timing recovery

Life of this patent

Sampled amplitude read channel employing interpolated timing recovery

Life of this patent

Abstract

Claims14