Loading patent…
AssigneeQUALCOMM Incorporated
InventorBenjamin E. Nise
Estimating the term…
The clock multiplying phase locked loop includes components for selectively setting a center frequency of a voltage controlled oscillator (VCO) to bias the VCO for operation within a selected range of input frequencies. To this end, the VCO is configured to output a signal at a selected center frequency based upon a tuning current provided to the VCO. Initially, a voltage input of the VCO is set to a reference voltage and a feedback signal is generated. The feedback signal, perhaps divided by N, is input to a phase-frequency detector. The phase-frequency detector also receives a reference frequency signal having a frequency at the selected center frequency. The detector outputs an UP or DOWN signal indicating whether the feedback signal is greater or less than the reference frequency signal. A center frequency adjustment unit receives the UP or DOWN signals from the detector and adjusts the tuning current to modify the center frequency of the VCO to reduce any difference between the feedback frequency and the reference frequency received by the phase-frequency detector. The VCO, the detector and the adjustment unit, as well as other components, operate in a loop causing the center frequency of the VCO to be iteratively adjusted until the center frequency approximates the selected center frequency to a selected degree of resolution. At that point, the voltage reference signal is disconnected from the voltage input of the VCO and the frequency reference signal is disconnected from the input of the phase-frequency detector, thus allowing the clock multiplier to operate as a phase locked loop (PLL). The tuning current, however, continues to be applied to the VCO to maintain the center frequency of the VCO at the selected center frequency such that further operation of the VCO is biased to that center frequency. Method and apparatus embodiments of the invention are disclosed.
In a clock multiplier having a phase-locked loop including a phase-frequency detector and a voltage controlled oscillator wherein the voltage control oscillator outputs a signal having a frequency at some multiple of an input frequency received by the phase-frequency detector based upon a center frequency, an improvement directed to setting a center frequency of the voltage controlled oscillator, said improvement comprising:
A method for setting a voltage controlled oscillator to a selected center frequency for use within a clock multiplier containing the voltage controlled oscillator and phase-frequency detector configured within a feedback loop, said method comprising the steps of:
A clock multiplying phase lock looped circuit comprising:
A clock multiplier circuit comprising:
Dependencies are inferred from the claim text.