Self-timed interface for a network of computer processors interconnected in parallel

A network of computer processors interconnected in parallel comprising in combination:

• a plurality of computer processors each of which functions as a data transmitter and as a data receiver and each of which has a processor clock signal;
• each of said plurality of computer processors including a self-timed interface for connecting said each of said plurality of computer processors in said network to each other computer processor in said network;
• said self-timed interface including transmitting means for transmitting digital data bytes with each bit of a byte coupled in parallel respectively to a separate line of a parallel data bus synchronously with a transmit clock signal which is independent of the processor clock signal and further including receiving means for receiving said data bytes and said transmit clock signal over said parallel data bus,
• said bus including a separate line for transmitting said clock signal,
• said receiving means including means to individually phase delay each bit on each said separate line with respect to said clock signal received by said receiving means, and
• a plurality of self-timed interface switching modules, each said switching module providing an internal cross-connection between external communication ports and a group of processor nodes connected to each of said plurality of self-timed interface switching modules and said self-timed interface connecting said external communications ports to said plurality of self-timed interface switching modules.