Instruction breakpoint detection apparatus for use in an out-of-order microprocessor

A microprocessor comprising:

• an instruction execution block to execute instructions;
• an instruction fetch and decode block coupled to communicate with said instruction execution block, said instruction fetch and decoding block to fetch and decode instruction data for providing said instructions to said instruction execution block;
• and
• an instruction break point detection apparatus incorporated within said instruction fetch and decode block, said instruction breakpoint detection apparatus comprising:
• a memory element to store a linear breakpoint address;
• an instruction fetch mechanism to retrieve a packet of aligned instruction data in accordance with a provided fetch instruction pointer, said packet of aligned instruction data including (N) bytes;
• a comparing circuit coupled to said instruction fetch mechanism and in communication with said memory element, said comparing circuitry to compare said fetch instruction pointer to said linear breakpoint address;
• and
• a byte marking circuit, coupled and responsive to said comparing circuit, to generate a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said packet of aligned instruction data, and identifying at least one byte of said packet of aligned instruction data as a code breakpoint, said breakpoint marking sequence being generated responsive to a match between at least a portion of said fetch instruction and at least a portion of said linear breakpoint address.

A computer system comprising:

• a bus;
• a main memory, coupled to said bus to store digital data;
• and a microprocessor, coupled to said bus, to process said digital data, said microprocessor comprising:
• an instruction fetch and decode block coupled to communicate with an execution block, said instruction fetch and decode block to fetch and decode instruction data for providing said instructions to said instruction execution block;
• and
• an instruction break point detection apparatus incorporated within said instruction fetch and decode block, said instruction breakpoint detection apparatus comprising:
• a memory element to store a linear breakpoint address;
• an instruction fetch mechanism to retrieve a packet of aligned instruction data in accordance with a provided fetch instruction pointer, said packet of aligned instruction data including (N) bytes;
• a comparing circuit coupled to said instruction fetch mechanism and in communication with said memory element, said comparing circuit to compare said fetch instruction pointer to said linear breakpoint address;
• and
• a byte marking circuit, coupled and responsive to said comparing circuit, to generate a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said packet of aligned instruction data, and identifying at least one byte of said packet of aligned instruction data as a code breakpoint, said breakpoint marking sequence being generated responsive to a match between at least a portion of said fetch instruction and at least a portion of said linear breakpoint address.

A method of detecting instruction code breakpoints comprising the steps of:

• storing a breakpoint address in a memory element;
• fetching an aligned packet of (N) bytes of instruction data based on a fetch instruction pointer;
• comparing the fetch instruction pointer to the breakpoint address;
• generating a breakpoint marking sequence including (N) bits, each of which is associated with a respective byte of said aligned packet, and identifying at least one byte of said (N) bytes of said aligned packet as a code breakpoint, if said comparing step produces a match between at least a portion of said fetch instruction pointer and at least a portion of said breakpoint address.