Apparatus and method for synchronizing data transfers in a single instruction multiple data processor

A processing system for receiving input data words, processing a plurality of the received data words in parallel and outputting processed data, comprising:

• a data input register for receiving and storing the input data words, said input register having a serial input port and a first parallel data port, such that the data words are received via said serial input port in a serial manner in response to a write clock and stored so as to be accessible via said first parallel port in a parallel manner in response to a processor clock;
• a plurality of processing elements, each for processing one of said data words in accordance with a predetermined processing algorithm to form processed data, said plurality of processing elements being connected to said first parallel port so that a different one of said input data words can be transferred from said data input register to each one of said plurality of processing elements using said processor clock for processing thereof by said predetermined processing algorithm;
• a data output register connected to each of said processing elements for receiving and storing said processed data from each of said processing elements using said processor clock, said output register having a second parallel data port and a serial output port, such that processed data can be transferred from said processing elements to said output register via said parallel port in a parallel manner and stored so as to be accessible for output via said serial output port in a serial manner in response to a read clock;
• a first sync circuit for synchronizing the operation of said data input register to the operation of an external device connected to said input register by forming said write clock, said first sync circuit being responsive to and synchronized with said input data;
• a second sync circuit for synchronizing the operation of said data output register with the operation of an external device connected to said output register by forming said read clock, said second sync circuit being separate and independent of said first sync circuit, said processor clock operating asynchronously from at least one of said read clock and said write clock;
• and
• an interrupt circuit being responsive to said first sync circuit and said second sync circuit for interrupting the processing operation of said processing element, thereby initiating an interruptive transfer of data between said processing element and at least one of said input and output registers.

A method for processing input data, comprising the steps of:

• receiving and storing input data in a data input register in a serial manner using a write clock;
• providing a processor;
• transferring data in parallel from the input data register to the processor for processing in a first transfer step using a processor clock;
• processing the data with the processor in accordance with a predetermined processing algorithm to form processed data therefrom;
• transferring the processed data output by the processor in a second transfer step to a data output register using said processor clock for storage therein;
• outputting the processed data therefrom in a serial manner using a read clock;
• generating a first sync signal in synchronism with an external device connected to said input register and synchronizing said write clock and the operation of the receiving stop to the first sync signal;
• independently generating a second sync signal in synchronism with an external device connected to said output register and synchronizing said read clock and the operation of the outputting step to the second sync signal, the first sync signal and the second sync signal operating asynchronously, wherein said processor clock operates asynchronously from at least one of said read clock and said write clock;
• and
• interrupting the processing operation of the processor in response to at least one of said first and second sync signals to initiate at least one of the first and second transfer steps.