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US 5,694,585 AGranted
Programmable memory controller and data terminal equipment
AssigneeInternational Business Machines Corporation
InventorsDavid Dwin, William Robert Lee, David William Nuechterlein
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Abstract
A programmable memory controller includes a plurality of multi-bit registers, with each multi-bit register coupled to a cycle generator. Each cycle generator is formed from a multi-bit shift register and control signals which drive each multi-bit shift register so that data in an associated multi-bit register is shifted through the shift register to form desired memory control pulses.
Claims12
A device for generating Memory Control Signals comprising:
- a Pattern Register array including a plurality of multistage registers each one being operable for storing bit patterns to be used to generate memory cycle control pulses;
- a first means for loading the bit patterns into the registers;
- a Cycle Generator array including a plurality of cycle generators wherein each of the plurality of cycle generators is coupled to a separate one of the plurality of multistage registers and each of said plurality of cycle generators including a plurality of shifters interconnected in shift register configuration with each shifter including a latch and a MUX with a latch input connected to the MUX;
- and
- a Cycle Control State Machine having an output coupled to the MUX in each shifter and generating proper shift control signals wherein desired memory control pulses are outputted from one of the latch.
2 more elements
Dependencies are inferred from the claim text.