Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation

A method of reducing computational requirements for executing simulation code for a transistor circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the transistor circuit design being subject to resistive conflicts and to charge sharing, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules, the method comprising, by computer generating a three-state version of simulation code for the transistor circuit design, said three-state version of simulation code having three states corresponding to states 0, 1, or X, where X represents an invalid or undefined state, said undefined state including representation of effects resulting from said resistive conflicts and said charge sharing,

• performing a preanalysis of the three-state version of simulation code and storing phase waveforms each representing values occurring at a node of the transistor circuit design,
• determining from said phase waveforms, each phase of a module for which no event-based evaluation need be performed,
• storing for said each phase of a module for which no event-based evaluation need be performed, an appropriate response to an event occurring with respect to the module of the three state version of simulation code,
• generating a two-state version of simulation code for the transistor circuit design, the two states corresponding to 0, and 1,
• executing said two-state version of simulation code for each phase of a module for which no event-based evaluation need be performed, using as said data structures for said two-state version of simulation code the stored response from said three-state version of simulation code.