Method and apparatus for performing load operations in a computer system

A method for performing operations with a processor in a computer system, said method comprising the steps of:

• storing in a storage area in the processor a plurality of load operations that have been blocked from execution completion due to at least an address or resource dependency conflict;
• maintaining, for each entry in the storage area, a tail pointer output indicating whether an individual load operation is the oldest load operation in the storage area and a ready signal output indicating if an individual load operation is ready for dispatch;
• determining whether each of the plurality of load operations is ready for dispatch to memory, wherein the step of determining comprises the steps of
• receiving an event producing at least one non-blocking indication,
• matching said event to a block code associated and stored with one of the plurality of load operations, wherein the one load operation is determined to be ready if said event matches the block code;
• setting ready signal outputs for each entry in the storage area in response to determining whether each of the plurality of load operations is ready for dispatch to memory,;
• scheduling the one load operation for dispatch to memory in response to ready signal and tail pointer outputs for each entry of the storage area;
• and
• dispatching the one load operation to memory.

A processor comprising:

• an issue unit that issues memory operations;
• a memory execution unit coupled to the issue unit to perform the memory operations;
• wherein the memory execution unit comprises
• means for storing in the processor a plurality of load operations that have been blocked from execution completion due to at least an address or resource dependency conflict, wherein each entry in the means for storing comprises a ready signal output indicating if an individual load operation is ready for dispatch and a tail pointer output indicating whether an individual load operation is the oldest load operation in the means for storing, wherein the means for storing has an output to provide one of the plurality of load operations;
• means for determining whether each of the plurality of load operations is ready for dispatch to memory by determining whether the address or resource dependency conflict causing each individual load operation in the plurality of load operations to be blocked no longer remains, wherein said means for determining has outputs coupled to the means for storing and indicative of the status of the plurality of load operations;
• means for scheduling one load operation of the plurality of load operations for dispatch to memory based on status of the plurality of load operations that includes ready signal and tail pointer outputs indicating that said one load operation is ready for dispatch, wherein the means for scheduling provides an indication to the means for storing indicating that said one load operation in the load buffer is scheduled for dispatch to memory;
• and
• means for dispatching the one load operation to memory.

A processor comprising:

• a load buffer storing a plurality of load operations that have been blocked due to at least a resource or address dependency, wherein the load buffer has an output of one of the plurality of load operations;
• a blocking logic coupled to the load buffer having signal inputs indicative of address and resource conflicts corresponding to the plurality of load operations and having outputs coupled to the lead buffer and indicative of the status of the plurality of lead operations;
• a scheduler coupled to provide an indication to the lead buffer that said one lead operation in the lead buffer is scheduled for dispatch to memory based on status of the plurality of lead operations;
• and
• a multiplexor having a first input coupled to receive the one load operation from the load buffer, a second input coupled to receive a new lead operation dispatched from a dispatch station and an output of either the one load operation or the new load operation.