Direct-mapped cache with cache locking allowing expanded contiguous memory storage by swapping one or more tag bits with one or more index bits
AssigneeIntegrated Device Technology, Inc.
InventorsPhilip A. Bourekas, Andrew P. Ng
Life of this patent
Estimating the term…
Abstract
A direct mapped cache with cache locking according to one embodiment of the present invention includes a physical address latch and a multiplexing means. The multiplexing means receives the physical address from the physical address latch and exchanges a physical address tag bit with a physical address index bit to generate a cache tag address and a cache index address to divide the cache into two halves, each half servicing a contiguous address range of main memory.
Claims20
A direct mapped cache memory for servicing an address space, said cache memory comprising:
- a memory for storing a data word and a tag at a cache index address in said memory;
- an address latch for receiving an address signal corresponding to an address in said address space, said address signal including an address tag signal and an address index signal;
- a multiplexer circuit, coupled to said memory and said address latch, for receiving a first component signal from said address tag signal and a second component signal from said address index signal and selectably exchanging said first component signal with said second component signal in response to a first control signal to form a cache tag signal that includes said second component signal and a cache index signal that includes said first component signal, whereby said cache index signal accesses a corresponding cache index address and causes said memory to generate a stored data signal and stored cache tag signal corresponding to said data word and said tag stored at said corresponding cache index address;
- and
- a tag comparator, coupled to said address latch and said memory, for comparing said cache tag signal with said stored cache tag signal.
A method for implementing a direct mapped cache memory for servicing an address space, said cache memory comprising a memory, said method comprising the steps of:
- receiving an address signal from a CPU, said address signal including an address tag signal and an address index signal;
- exchanging a first component signal of said address tag signal with a second component signal of said address index signal;
- providing a cache index signal that includes said first component signal;
- providing a cache tag signal that includes said second component signal;
- accessing a cache index address of said memory with said cache index signal to provide a data word signal and a stored tag signal corresponding to a data word and tag stored in said memory at said cache index address;
- and
- comparing said cache tag signal with said stored tag signal and generating a match signal when said cache tag signal and said stored tag signal match.
A direct mapped cache memory, for servicing an address space, said cache memory comprising:
- a memory;
- receiving means for receiving an address signal from a CPU, said address signal including an address tag signal and an address index signal;
- exchanging means, coupled to said receiving means, for exchanging a first component signal of said address tag signal with a second component signal of said address index signal;
- cache index means, coupled to said exchanging means, for providing a cache index signal that includes said first component signal;
- cache tag means, coupled to said exchanging means, for providing a cache tag signal that includes said second component signal;
- accessing means, coupled to said cache index means and said memory, for accessing a cache index address of said memory with said cache index signal to provide a data word signal and a stored tag signal corresponding to a data word and tag stored in said memory at said cache index address;
- and
- comparing means, coupled to said cache tag means and said memory, for comparing said cache tag signal with said stored tag signal and generating a match signal when said cache tag signal and said stored tag signal match.
Dependencies are inferred from the claim text.