Time multiplexing address and data on an existing PC parallel port

A method of communicating with peripheral devices via a personal computer parallel port comprising multiplexing a data bus connected to the parallel port between address data, computer data for writing to an addressed peripheral device, and peripheral data received from the addressed peripheral device, and providing control signals signifying states defining which of said address data, computer data or said peripheral data is to be carried by the data bus.

A bus interface for interconnecting a computer data bus with a peripheral device, comprising a multiplexer having a computer data bus port, a peripheral data bus port and a peripheral address bus port, the multiplexer including means for receiving an address control signal and in response passing data appearing at the computer data bus port to the peripheral address bus port, the multiplexer including means for receiving a write control signal and in response passing data appearing at the computer data bus port to the peripheral data bus port, and the multiplexer including means for receiving a read control signal and in response passing data appearing at the peripheral data bus port to the computer data bus port.