Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit

A method of analyzing at least a portion of an integrated circuit (IC) comprising the of automatically:

• (a) scanning at least a portion of a layer of an integrated circuit using high magnification to provide first digital signals representing pixel amplitudes,
• (b) extracting features of interest representative of IC mutual interconnection locations between layers from the first digital signals to provide second digital signals representing values of groups of pixels defining said features of interest;
• (c) modifying said second digital signals representing adjacent features of interest from step (b) so as to mosaic the features of interest and providing third signals representing a seamless representation of said layer by
• (i) selecting data representing a set of four images representing adjacent features of interest,
• (ii) computing mutually orthogonal (x,y) coordinate offsets between two adjacent images in each said set of four images which minimizes registration error between image pairs,
• (iii) determining, from computation of said offsets, whether a sufficient number of unique x, y coordinate offsets exists to define a cell, and in the event there is an insufficient number, indirectly determining missing x, y offset,
• (iv) subtracting said offsets and computing overlap between image pairs in said set of four images after subtracting said offsets,
• whereby a cell representation signal of said four images is obtained as representations of said adjacent features of interest,
• (d) repeating steps (a), (b) and (c) for other layers of the integrated circuit, whereby plural third signals representing plural ones of said layers are provided,
• (e) registering said plural third signals relative to each other so as to represent vertical alignment of said layers, and establishing an integrated circuit layout database therefrom, and
• (f) generating a schematic diagram of a circuit contained in the integrated circuit from the said database.

A method of analyzing at least a portion of an integrated circuit comprising the steps of automatically:

• (a) scanning small portions of at least a portion of a layer of an IC using high magnification, to obtain stored images of said portions of the IC,
• (b) converting said stored images to polygon data
• (c) assembling the polygon data in mosaicked image sets,
• (d) repeating steps (a), (b) and (c) for plural layers of the IC,
• (e) registering the mosaicking image sets into alignment, and
• (f) generating a schematic diagram of circuitry represented by at least a portion of the IC from the aligned mosaicked image sets,
• in which step (c) is comprised of:
• (i) selecting data representing a set of four images representing adjacent features of interest,
• (ii) computing mutually orthogonal (x,y) coordinate offsets between two adjacent images in said set of four images which minimizes registration error between image pairs, and
• (iii) substracting said offsets and computing overlap between image pairs in said set of four images after substracting said offsets,
• whereby a cell representation signal of said four images is obtained as representations of said adjacent features of interest.

A method of analyzing at least a portion of an integrated circuit which has been scanned, and images adjacent or overlapping regions of the integrated circuit stored, comprising the steps of:

• (i) selecting data representing a set of four images representing adjacent features of interest,
• (ii) computing mutually orthogonal (x,y) coordinate offsets between two adjacent images in said set of four images which minimizes registration error between image pairs,
• (iii) subtracting said offsets and computing overlap between image pairs in said set of four images after subtracting said offsets,
• whereby a cell representation signal of said four images is obtained as representations of said adjacent features of interest,
• (iv) determining, from computation of said offsets, whether of sufficient number of unique x, y coordinate offsets exists to define a cell, and in the event there is an insufficient number, indirectly determining missing x, y offsets prior to step (iii).